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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2002/08/19 16:54:25 mihad
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// Revision 1.4 2002/08/19 16:54:25 mihad
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// Got rid of undef directives
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// Got rid of undef directives
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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// only host implementation has access for generating interrupt acknowledge and configuration cycles
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// only host implementation has access for generating interrupt acknowledge and configuration cycles
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// configuration cycle data register hit
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// configuration cycle data register hit
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reg current_delayed_is_ccyc ;
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reg current_delayed_is_ccyc ;
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reg current_delayed_is_iack ;
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reg current_delayed_is_iack ;
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wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) && alligned_address ;
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wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
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wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) && alligned_address ;
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wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
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reg iack_hit ;
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reg iack_hit ;
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reg ccyc_hit ;
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reg ccyc_hit ;
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always@(posedge reset_in or posedge wb_clock_in)
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always@(posedge reset_in or posedge wb_clock_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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Line 866... |
end // S_READ
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end // S_READ
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S_CONF_WRITE: begin
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S_CONF_WRITE: begin
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`ifdef HOST
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`ifdef HOST
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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del_req = do_ccyc_req && ~burst_transfer && alligned_address ;
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del_req = do_ccyc_req && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
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del_done = do_ccyc_comp && ~burst_transfer && alligned_address ;
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del_done = do_ccyc_comp && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
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del_in_progress = do_ccyc_comp && ~burst_transfer && alligned_address ;
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del_in_progress = do_ccyc_comp && ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif ;
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`endif
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`endif
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n_state = S_IDLE ; // next state after configuration access is always idle
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n_state = S_IDLE ; // next state after configuration access is always idle
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if ( burst_transfer || ~alligned_address )
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if ( burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else | ~alligned_address `endif )
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begin
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begin
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err = 1'b1 ;
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err = 1'b1 ;
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end
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end
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else
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else
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begin
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begin
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end // S_CONF_WRITE
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end // S_CONF_WRITE
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S_CONF_READ: begin
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S_CONF_READ: begin
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`ifdef HOST
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`ifdef HOST
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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wbw_data_out_sel = SEL_CCYC_ADDR ;
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del_req = ~burst_transfer && alligned_address && ( do_ccyc_req || do_iack_req );
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del_req = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_req || do_iack_req ) ;
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del_done = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
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del_done = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
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del_in_progress = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
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del_in_progress = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
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wbr_fifo_renable = ~burst_transfer && alligned_address && ( do_ccyc_comp || do_iack_comp ) ;
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wbr_fifo_renable = ~burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else && alligned_address `endif && ( do_ccyc_comp || do_iack_comp ) ;
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`endif
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`endif
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n_state = S_IDLE ; // next state after configuration access is always idle
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n_state = S_IDLE ; // next state after configuration access is always idle
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if ( burst_transfer || ~alligned_address )
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if ( burst_transfer `ifdef PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS `else | ~alligned_address `endif )
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begin
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begin
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err = 1'b1 ;
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err = 1'b1 ;
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end
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end
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else
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else
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begin
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begin
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