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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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//
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//
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// Revision 1.7 2002/10/17 22:49:22 tadejm
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// Revision 1.7 2002/10/17 22:49:22 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.6 2002/10/11 10:09:01 mihad
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// Revision 1.6 2002/10/11 10:09:01 mihad
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| Line 163... |
Line 166... |
wbu_ad_load_on_transfer_out
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wbu_ad_load_on_transfer_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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mbist_si_i, // bist scan serial in
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scanb_clk, // bist scan clock
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mbist_so_o, // bist scan serial out
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scanb_si, // bist scan serial in
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mbist_ctrl_i // bist chain shift control
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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| Line 274... |
Line 275... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input scanb_rst; // bist scan reset
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input mbist_si_i; // bist scan serial in
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input scanb_clk; // bist scan clock
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output mbist_so_o; // bist scan serial out
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input scanb_si; // bist scan serial in
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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// pci master interface outputs
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// pci master interface outputs
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wire [31:0] pcim_if_address_out ;
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wire [31:0] pcim_if_address_out ;
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wire [3:0] pcim_if_bc_out ;
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wire [3:0] pcim_if_bc_out ;
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| Line 582... |
Line 581... |
.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_flush_in (fifos_wbr_flush_in),
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.wbr_empty_out (fifos_wbr_empty_out)
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.wbr_empty_out (fifos_wbr_empty_out)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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) ;
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) ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire [31:0] amux_addr_in = ADDR_I ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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wire amux_sample_address_in = wbs_sm_sample_address_out ;
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