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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_wbw_wbr_fifos.v] - Diff between revs 88 and 111
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Rev 111 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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//
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// Revision 1.2 2003/01/30 22:01:09 mihad
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// Revision 1.2 2003/01/30 22:01:09 mihad
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// Updated synchronization in top level fifo modules.
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// Updated synchronization in top level fifo modules.
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//
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
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end
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end
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wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
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wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
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reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
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reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
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synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
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pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
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(
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(
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.data_in (inGreyCount),
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.data_in (inGreyCount),
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.clk_out (pci_clock_in),
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.clk_out (pci_clock_in),
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.sync_data_out (pci_clk_sync_inGreyCount),
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.sync_data_out (pci_clk_sync_inGreyCount),
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.async_reset (wbw_clear)
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.async_reset (wbw_clear)
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