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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/08/14 13:06:03 simons
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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//
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// Revision 1.4 2003/08/08 16:36:33 tadejm
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// Revision 1.4 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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//
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//
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// Revision 1.3 2003/03/26 13:16:18 mihad
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// Revision 1.3 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added the reset value parameter to the synchronizer flop module.
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Line 58... |
//
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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//
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//
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Revision 1.8 2002/10/11 10:09:01 mihad
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| Line 130... |
Line 133... |
pcir_transaction_ready_out
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pcir_transaction_ready_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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mbist_si_i, // bist scan serial in
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scanb_clk, // bist scan clock
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mbist_so_o, // bist scan serial out
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scanb_si, // bist scan serial in
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mbist_ctrl_i // bist chain shift control
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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`endif
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) ;
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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System inputs:
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| Line 251... |
Line 252... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input scanb_rst; // bist scan reset
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input mbist_si_i; // bist scan serial in
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input scanb_clk; // bist scan clock
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output mbist_so_o; // bist scan serial out
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input scanb_si; // bist scan serial in
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Address length parameters:
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Address length parameters:
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PCIW_DEPTH = defines PCIW_FIFO depth
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PCIW_DEPTH = defines PCIW_FIFO depth
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| Line 379... |
Line 378... |
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wire pciw_read_enable = 1'b1 ;
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wire pciw_read_enable = 1'b1 ;
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wire pcir_read_enable = 1'b1 ;
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wire pcir_read_enable = 1'b1 ;
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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wire scanb_so_internal ; // wires for connection of debug ports on two rams
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wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
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wire scanb_si_internal = scanb_so_internal ;
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wire mbist_si_i_internal = mbist_so_o_internal ;
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`endif
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`endif
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// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
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// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
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pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
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pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
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(
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(
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| Line 407... |
Line 406... |
.di_b(40'h00_0000_0000),
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.di_b(40'h00_0000_0000),
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.do_b(dpram_portB_output)
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.do_b(dpram_portB_output)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o_internal),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so_internal),
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
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pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
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(
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(
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| Line 438... |
Line 435... |
.di_b(40'h00_0000_0000),
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.di_b(40'h00_0000_0000),
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.do_b(dpram_portA_output)
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.do_b(dpram_portA_output)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i_internal),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si_internal),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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`else // RAM blocks sharing between two fifos
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`else // RAM blocks sharing between two fifos
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Line 496... |
.di_b(dpram_portB_input),
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.di_b(dpram_portB_input),
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.do_b(dpram_portB_output)
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.do_b(dpram_portB_output)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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`endif
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`endif
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