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[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [pci_perr_en_crit.v] - Diff between revs 77 and 83
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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non_critical_par_in,
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non_critical_par_in,
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pci_par_in,
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pci_par_in,
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perr_generate_in,
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perr_generate_in,
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par_err_response_in ;
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par_err_response_in ;
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wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^^ pci_par_in ) ;
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wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^ pci_par_in ) ;
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// PERR# is enabled for two clocks after parity error is detected - one cycle active, another inactive
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// PERR# is enabled for two clocks after parity error is detected - one cycle active, another inactive
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reg perr_en_reg_out ;
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reg perr_en_reg_out ;
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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