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[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [pci_target_unit.v] - Diff between revs 2 and 6
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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//
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// Module instantiates and connects other modules lower in hierarcy
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// Module instantiates and connects other modules lower in hierarcy
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// PCI target unit consists of modules that together form datapath
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// PCI target unit consists of modules that together form datapath
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// between external WISHBONE slaves and external PCI initiators
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// between external WISHBONE slaves and external PCI initiators
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`include "constants.v"
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`include "constants.v"
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`include "timescale.v"
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module PCI_TARGET_UNIT
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module PCI_TARGET_UNIT
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(
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(
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reset_in,
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reset_in,
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wb_clock_in,
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wb_clock_in,
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