| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/08/14 13:06:03 simons
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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//
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//
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// Revision 1.6 2002/10/17 22:49:22 tadejm
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// Revision 1.6 2002/10/17 22:49:22 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Revision 1.5 2002/10/11 10:09:01 mihad
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| Line 113... |
Line 116... |
di_b,
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di_b,
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do_b
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do_b
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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mbist_si_i, // bist scan serial in
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scanb_clk, // bist scan clock
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mbist_so_o, // bist scan serial out
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scanb_si, // bist scan serial in
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mbist_ctrl_i // bist chain shift control
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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| Line 149... |
Line 150... |
input [dw-1:0] di_b; // input data bus
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input [dw-1:0] di_b; // input data bus
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output [dw-1:0] do_b; // output data bus
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output [dw-1:0] do_b; // output data bus
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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// debug chain signals
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// debug chain signals
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input scanb_rst; // bist scan reset
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input mbist_si_i; // bist scan serial in
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input scanb_clk; // bist scan clock
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output mbist_so_o; // bist scan serial out
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input scanb_si; // bist scan serial in
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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| Line 179... |
Line 178... |
.REN (1'b0),
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.REN (1'b0),
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.WEN (!we_a)
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.WEN (!we_a)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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assign do_a = 0 ;
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assign do_a = 0 ;
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`endif
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`endif
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| Line 214... |
Line 211... |
.CENB(~ce_b),
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.CENB(~ce_b),
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.WENB(~we_b),
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.WENB(~we_b),
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.AB(addr_b),
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.AB(addr_b),
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.DB(di_b),
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.DB(di_b),
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.OENB(~oe_b),
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.OENB(~oe_b),
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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);
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);
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`else
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`else
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art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
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art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
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(
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(
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.QA(do_a),
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.QA(do_a),
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