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[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [timescale.v] - Diff between revs 6 and 21
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/10/05 08:11:22 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// timescale directive is included in all core's modules for simulation purposes
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// timescale directive is included in all core's modules for simulation purposes
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`timescale 1ns/10ps
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`timescale 1ns/1ps
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