| Line 15... |
Line 15... |
-DEFINE WB_CLK66
|
-DEFINE WB_CLK66
|
-DEFINE ACTIVE_HIGH_OE
|
-DEFINE ACTIVE_HIGH_OE
|
-DEFINE WB_CNF_BASE_ZERO
|
-DEFINE WB_CNF_BASE_ZERO
|
-DEFINE NO_CNF_IMAGE
|
-DEFINE NO_CNF_IMAGE
|
-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
|
-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
|
-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS
|
|
../../../rtl/verilog/pci_parity_check.v
|
../../../rtl/verilog/pci_parity_check.v
|
../../../rtl/verilog/pci_target_unit.v
|
../../../rtl/verilog/pci_target_unit.v
|
../../../rtl/verilog/pci_wb_addr_mux.v
|
../../../rtl/verilog/pci_wb_addr_mux.v
|
../../../rtl/verilog/pci_cbe_en_crit.v
|
../../../rtl/verilog/pci_cbe_en_crit.v
|
../../../rtl/verilog/pci_pcir_fifo_control.v
|
../../../rtl/verilog/pci_pcir_fifo_control.v
|
| Line 60... |
Line 59... |
../../../rtl/verilog/pci_delayed_write_reg.v
|
../../../rtl/verilog/pci_delayed_write_reg.v
|
../../../rtl/verilog/pci_mas_ad_en_crit.v
|
../../../rtl/verilog/pci_mas_ad_en_crit.v
|
../../../rtl/verilog/pci_mas_ad_load_crit.v
|
../../../rtl/verilog/pci_mas_ad_load_crit.v
|
../../../rtl/verilog/pci_master32_sm.v
|
../../../rtl/verilog/pci_master32_sm.v
|
../../../rtl/verilog/pci_target32_stop_crit.v
|
../../../rtl/verilog/pci_target32_stop_crit.v
|
../../../rtl/verilog/synchronizer_flop.v
|
../../../rtl/verilog/pci_synchronizer_flop.v
|
../../../rtl/verilog/pci_async_reset_flop.v
|
../../../rtl/verilog/pci_async_reset_flop.v
|
../../../rtl/verilog/pci_mas_ch_state_crit.v
|
../../../rtl/verilog/pci_mas_ch_state_crit.v
|
../../../rtl/verilog/pci_master32_sm_if.v
|
../../../rtl/verilog/pci_master32_sm_if.v
|
../../../rtl/verilog/pci_target32_trdy_crit.v
|
../../../rtl/verilog/pci_target32_trdy_crit.v
|
../../../rtl/verilog/top.v
|
../../../rtl/verilog/top.v
|
| Line 82... |
Line 81... |
../../../bench/verilog/pci_behaviorial_target.v
|
../../../bench/verilog/pci_behaviorial_target.v
|
../../../bench/verilog/wb_slave_behavioral.v
|
../../../bench/verilog/wb_slave_behavioral.v
|
../../../bench/verilog/wb_bus_mon.v
|
../../../bench/verilog/wb_bus_mon.v
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
|
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
|
../../../../../../lib/xilinx/lib/glbl/glbl.v
|
|
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
|
|
../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
|
|
../../../rtl/verilog/pci_ram_16x40d.v
|
|
