URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Diff between revs 104 and 106

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Rev 104	Rev 106
Line 20...	Line 20...
`set arg_xilinx = 0;`	`set arg_xilinx = 0;`
`set arg_artisan = 0;`	`set arg_artisan = 0;`
`set arg_waves = 0;`	`set arg_waves = 0;`
`set arg_vs_hdtp = 0`	`set arg_vs_hdtp = 0`
`set arg_dis_comp_exp_test = 0`	`set arg_dis_comp_exp_test = 0`
	`set arg_wb_b3 = 0`
	`set arg_wbs_non_alligned = 0`

`@ arg_num = 1`	`@ arg_num = 1`
`set arg_check = 0`	`set arg_check = 0`

`while($arg_num <= $#argv)`	`while($arg_num <= $#)`
`if ($argv[$arg_num] == "help") then`
	`switch ( $argv[$arg_num] )`
	`case "help":`
`goto help`	`goto help`
`endif`	`breaksw`

`if ($argv[$arg_num] == "regression") then`	`case "regression":`
`@ arg_regression = 1`	`@ arg_regression = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`

`if ($argv[$arg_num] == "xilinx") then`	`case "xilinx":`
`@ arg_xilinx = 1`	`@ arg_xilinx = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`

`if($argv[$arg_num] == "artisan") then`	`case "artisan":`
`@ arg_artisan = 1`	`@ arg_artisan = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`

`if ($argv[$arg_num] == "waves") then`	`case "waves":`
`@ arg_waves = 1`	`@ arg_waves = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`

`if ($argv[$arg_num] == "vs_two_port") then`	`case "vs_two_port":`
`@ arg_vs_hdtp = 1`	`@ arg_vs_hdtp = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`

`if ($argv[$arg_num] == "disable_completion_expired_tests") then`	`case "disable_completion_expired_tests":`
`@ arg_dis_comp_exp_test = 1`	`@ arg_dis_comp_exp_test = 1`
`@ arg_check = $arg_check + 1`	`breaksw`
`endif`
	`case "wb_b3":`
	`@ arg_wb_b3 = 1`
	`breaksw`

	`case "wb_na":`
	`@ arg_wbs_non_alligned = 1`
	`breaksw`

`if ($argv[$arg_num] == "iter") then`	`case "iter":`
`@ arg_num = $arg_num + 1`	`@ arg_num = $arg_num + 1`
`@ arg_check = $arg_check + 2`
`@ iter = $argv[$arg_num]`	`@ iter = $argv[$arg_num]`
`@ all_iterations = $iter`	`@ all_iterations = $iter`
`endif`	`breaksw`

`if ($arg_check != $arg_num) then`	`default:`
`echo "Invalid argument found: $argv[$arg_num]"`	`echo "Invalid argument!"`
`echo`
`goto help`	`goto help`
`endif`	`breaksw`
`@ arg_num = $arg_num + 1`	`endsw`

	`@ arg_num++`
`end`	`end`

`# ITERATION LOOP`	`# ITERATION LOOP`
`iteration:`	`iteration:`

Line 517...	Line 523...
`endif`	`endif`

`if ($arg_dis_comp_exp_test) then`	`if ($arg_dis_comp_exp_test) then`
`echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args`	`echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args`
`endif`	`endif`

	`if ($arg_wb_b3) then`
	`echo "-DEFINE PCI_WB_REV_B3" >> ./defines.args`
	`endif`

	`if ($arg_wbs_non_alligned) then`
	`echo "-DEFINE PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS" >> ./defines.args`
	`endif`

`endif`	`endif`
`endif`	`endif`


`# Run NC-Verilog compiler`	`# Run NC-Verilog compiler`
Line 592...	Line 607...
`else`	`else`
`echo "-input ../bin/ncsim.rc" >> ./ncsim.args`	`echo "-input ../bin/ncsim.rc" >> ./ncsim.args`
`endif`	`endif`
`echo "worklib.bridge32:fun" >> ./ncsim.args`	`echo "worklib.bridge32:fun" >> ./ncsim.args`

`ncsim -file ./ncsim.args #> /dev/null`	`ncsim -file ./ncsim.args > /dev/null`

`if ($status != 0) then`	`if ($status != 0) then`
`echo ""`	`echo ""`
`echo "TESTS couldn't start due to Errors!"`	`echo "TESTS couldn't start due to Errors!"`
`echo ""`	`echo ""`

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[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Diff between revs 104 and 106