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[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] [run_pci_sim_regr.scr] - Diff between revs 106 and 118
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| Rev 106 |
Rev 118 |
| Line 570... |
Line 570... |
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if ($arg_vs_hdtp == 1) then
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if ($arg_vs_hdtp == 1) then
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cat ../bin/vs_file_list.lst >> ./ncvlog.args
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cat ../bin/vs_file_list.lst >> ./ncvlog.args
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endif
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endif
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ncvlog -file ./ncvlog.args > /dev/null;
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ncvlog -file ./ncvlog.args #> /dev/null;
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echo ""
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echo ""
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# Run the NC-Verilog elaborator (build the design hierarchy)
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# Run the NC-Verilog elaborator (build the design hierarchy)
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echo ""
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echo ""
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echo "\t@@@"
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echo "\t@@@"
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echo "\t@@@ Building design hierarchy (elaboration)"
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echo "\t@@@ Building design hierarchy (elaboration)"
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echo "\t@@@"
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echo "\t@@@"
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if ($arg_xilinx == 1) then
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if ($arg_xilinx == 1) then
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ncelab -file ../bin/ncelab_xilinx.args > /dev/null;
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ncelab -file ../bin/ncelab_xilinx.args #> /dev/null;
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else
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else
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ncelab -file ../bin/ncelab.args > /dev/null;
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ncelab -file ../bin/ncelab.args #> /dev/null;
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endif
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endif
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echo ""
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echo ""
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# Run the NC-Verilog simulator (simulate the design)
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# Run the NC-Verilog simulator (simulate the design)
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| Line 607... |
Line 607... |
else
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else
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echo "-input ../bin/ncsim.rc" >> ./ncsim.args
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echo "-input ../bin/ncsim.rc" >> ./ncsim.args
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endif
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endif
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echo "worklib.bridge32:fun" >> ./ncsim.args
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echo "worklib.bridge32:fun" >> ./ncsim.args
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ncsim -file ./ncsim.args > /dev/null
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ncsim -file ./ncsim.args #> /dev/null
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if ($status != 0) then
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if ($status != 0) then
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echo ""
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echo ""
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echo "TESTS couldn't start due to Errors!"
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echo "TESTS couldn't start due to Errors!"
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echo ""
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echo ""
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