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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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Line 64... |
// It provides data flip flops with reset
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// It provides data flip flops with reset
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module pci_in_reg
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module pci_in_reg
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(
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(
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reset_in,
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reset_in,
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clk_in,
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clk_in,
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init_complete_in,
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pci_gnt_in,
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pci_gnt_in,
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pci_frame_in,
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pci_frame_in,
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pci_irdy_in,
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pci_irdy_in,
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pci_trdy_in,
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pci_trdy_in,
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| Line 84... |
Line 88... |
pci_ad_reg_out,
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pci_ad_reg_out,
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pci_cbe_reg_out
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pci_cbe_reg_out
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);
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);
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input reset_in, clk_in ;
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input reset_in, clk_in, init_complete_in ;
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input pci_gnt_in ;
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input pci_gnt_in ;
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input pci_frame_in ;
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input pci_frame_in ;
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input pci_irdy_in ;
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input pci_irdy_in ;
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input pci_trdy_in ;
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input pci_trdy_in ;
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Line 126... |
always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if ( reset_in )
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if ( reset_in )
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begin
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begin
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pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
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pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
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pci_frame_reg_out <= #`FF_DELAY 1'b1 ;
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pci_frame_reg_out <= #`FF_DELAY 1'b0 ;
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pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
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pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
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pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
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pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
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pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
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pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
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pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
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pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
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pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
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pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
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end
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end
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else
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else if (init_complete_in)
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begin
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begin
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pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
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pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
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pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
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pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
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pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
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pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
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pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
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pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
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