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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [async_reset_flop.v] - Diff between revs 18 and 32

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Rev 18 Rev 32
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//===========================================================================
//===========================================================================
// $Id: async_reset_flop.v,v 1.1 2002-02-01 14:43:31 mihad Exp $
// $Id: async_reset_flop.v,v 1.2 2002-02-25 15:15:43 mihad Exp $
//
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//// async_reset_flop                                             ////
//// async_reset_flop                                             ////
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// CVS Revision History
// CVS Revision History
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// Revision 1.1  2002/02/01 14:43:31  mihad
 
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// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
 
`include "pci_constants.v"
// synopsys translate_on
// synopsys translate_on
 
 
module async_reset_flop (
module async_reset_flop (
  data_in, clk_in, async_reset_data_out, reset_in
  data_in, clk_in, async_reset_data_out, reset_in
);
);

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