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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [bus_commands.v] - Diff between revs 21 and 53
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Rev 53 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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`define BC_MEM_READ_LN 4'hE // yes yes
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`define BC_MEM_READ_LN 4'hE // yes yes
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`define BC_MEM_WRITE_INVAL 4'hF // no yes
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`define BC_MEM_WRITE_INVAL 4'hF // no yes
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// common bits for configuration cycle commands
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// common bits for configuration cycle commands
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`define BC_CONF_RW 3'b101
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`define BC_CONF_RW 3'b101
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// common bits for io cycle commands
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`define BC_IO_RW 3'b001
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