| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
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// CVS Revision History
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//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/02/01 15:25:12 mihad
|
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
|
//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
|
//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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| Line 400... |
Line 403... |
`endif
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`endif
|
`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
|
`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
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reg [31 : 12] pci_ba0_bit31_12 ;
|
reg [31 : 12] pci_ba0_bit31_12 ;
|
wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support
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wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support
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wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
|
wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
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wire [31 : 12] pci_am0 = def_pci_image0_addr_map ; // 20'hffff_f ; // 4KBytes of configuration space
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wire [31 : 12] pci_am0 = 20'hFFFF_F ; // address mask for configuration image always 20'hffff_f
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wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
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wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
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`endif
|
`endif
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`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
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`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
|
reg [31 : 12] pci_ba0_bit31_12 ;
|
reg [31 : 12] pci_ba0_bit31_12 ;
|
wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch
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wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch
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wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
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wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space
|
wire [31 : 12] pci_am0 = def_pci_image0_addr_map ; // 20'hffff_f ; // 4KBytes of configuration space
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wire [31 : 12] pci_am0 = 20'hffff_f ; // address mask for configuration image always 20'hffff_f
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wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
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wire [31 : 12] pci_ta0 = 20'h0000_0 ; // NO address translation needed
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`endif
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`endif
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// IMAGE1 is included by default, meanwhile other IMAGEs are optional !!!
|
// IMAGE1 is included by default, meanwhile other IMAGEs are optional !!!
|
reg [2 : 1] pci_img_ctrl1_bit2_1 ;
|
reg [2 : 1] pci_img_ctrl1_bit2_1 ;
|
reg [31 : 12] pci_ba1_bit31_12 ;
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reg [31 : 12] pci_ba1_bit31_12 ;
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| Line 705... |
Line 708... |
4'h4:
|
4'h4:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba0_bit0 ;
|
r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
|
end
|
end
|
4'h5:
|
4'h5:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba1_bit0 ;
|
r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
|
end
|
end
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4'h6:
|
4'h6:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba2_bit0 ;
|
r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
|
end
|
end
|
4'h7:
|
4'h7:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba3_bit0 ;
|
r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
|
end
|
end
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4'h8:
|
4'h8:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba4_bit0 ;
|
r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
|
end
|
end
|
4'h9:
|
4'h9:
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba5_bit0 ;
|
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
|
end
|
end
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4'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
4'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
default : r_conf_data_out = 32'h0000_0000 ;
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default : r_conf_data_out = 32'h0000_0000 ;
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endcase
|
endcase
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end
|
end
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| Line 760... |
Line 763... |
`P_BA0_ADDR :
|
`P_BA0_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
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pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
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r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
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r_conf_data_out[0] = pci_ba0_bit0 ;
|
r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
|
end
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end
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`P_AM0_ADDR :
|
`P_AM0_ADDR :
|
begin
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begin
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r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
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r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
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r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
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r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
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| Line 778... |
Line 781... |
`P_BA1_ADDR :
|
`P_BA1_ADDR :
|
begin
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begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba1_bit0 ;
|
r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
|
end
|
end
|
`P_AM1_ADDR :
|
`P_AM1_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
| Line 796... |
Line 799... |
`P_BA2_ADDR :
|
`P_BA2_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba2_bit0 ;
|
r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
|
end
|
end
|
`P_AM2_ADDR :
|
`P_AM2_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
| Line 814... |
Line 817... |
`P_BA3_ADDR :
|
`P_BA3_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba3_bit0 ;
|
r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
|
end
|
end
|
`P_AM3_ADDR :
|
`P_AM3_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
| Line 832... |
Line 835... |
`P_BA4_ADDR :
|
`P_BA4_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba4_bit0 ;
|
r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
|
end
|
end
|
`P_AM4_ADDR :
|
`P_AM4_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
| Line 850... |
Line 853... |
`P_BA5_ADDR :
|
`P_BA5_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
r_conf_data_out[0] = pci_ba5_bit0 ;
|
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
|
end
|
end
|
`P_AM5_ADDR :
|
`P_AM5_ADDR :
|
begin
|
begin
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
|
| Line 1035... |
Line 1038... |
4'h4: // w_reg_select_dec bit 4
|
4'h4: // w_reg_select_dec bit 4
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba0_bit0 ;
|
w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
|
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
|
end
|
end
|
4'h5: // w_reg_select_dec bit 8
|
4'h5: // w_reg_select_dec bit 8
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba1_bit0 ;
|
w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
|
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
|
end
|
end
|
4'h6: // w_reg_select_dec bit 12
|
4'h6: // w_reg_select_dec bit 12
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba2_bit0 ;
|
w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
|
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
|
end
|
end
|
4'h7: // w_reg_select_dec bit 16
|
4'h7: // w_reg_select_dec bit 16
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba3_bit0 ;
|
w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
|
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
|
end
|
end
|
4'h8: // w_reg_select_dec bit 20
|
4'h8: // w_reg_select_dec bit 20
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba4_bit0 ;
|
w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
|
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
|
end
|
end
|
4'h9: // w_reg_select_dec bit 24
|
4'h9: // w_reg_select_dec bit 24
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba5_bit0 ;
|
w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
|
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
|
end
|
end
|
4'hf: // w_reg_select_dec bit 2
|
4'hf: // w_reg_select_dec bit 2
|
begin
|
begin
|
w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
|
| Line 1111... |
Line 1114... |
`P_BA0_ADDR: // w_reg_select_dec bit 4
|
`P_BA0_ADDR: // w_reg_select_dec bit 4
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba0_bit0 ;
|
w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
|
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for another address
|
end
|
end
|
`P_AM0_ADDR: // w_reg_select_dec bit 5
|
`P_AM0_ADDR: // w_reg_select_dec bit 5
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1136... |
Line 1139... |
`P_BA1_ADDR: // w_reg_select_dec bit 8
|
`P_BA1_ADDR: // w_reg_select_dec bit 8
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba1_bit0 ;
|
w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
|
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for another address
|
end
|
end
|
`P_AM1_ADDR: // w_reg_select_dec bit 9
|
`P_AM1_ADDR: // w_reg_select_dec bit 9
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1161... |
Line 1164... |
`P_BA2_ADDR: // w_reg_select_dec bit 12
|
`P_BA2_ADDR: // w_reg_select_dec bit 12
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba2_bit0 ;
|
w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
|
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for another address
|
end
|
end
|
`P_AM2_ADDR: // w_reg_select_dec bit 13
|
`P_AM2_ADDR: // w_reg_select_dec bit 13
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1186... |
Line 1189... |
`P_BA3_ADDR: // w_reg_select_dec bit 16
|
`P_BA3_ADDR: // w_reg_select_dec bit 16
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba3_bit0 ;
|
w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
|
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for another address
|
end
|
end
|
`P_AM3_ADDR: // w_reg_select_dec bit 17
|
`P_AM3_ADDR: // w_reg_select_dec bit 17
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1211... |
Line 1214... |
`P_BA4_ADDR: // w_reg_select_dec bit 20
|
`P_BA4_ADDR: // w_reg_select_dec bit 20
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba4_bit0 ;
|
w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
|
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0010_0000 ; // The same for another address
|
end
|
end
|
`P_AM4_ADDR: // w_reg_select_dec bit 21
|
`P_AM4_ADDR: // w_reg_select_dec bit 21
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1236... |
Line 1239... |
`P_BA5_ADDR: // w_reg_select_dec bit 24
|
`P_BA5_ADDR: // w_reg_select_dec bit 24
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
|
w_conf_data_out[0] = pci_ba5_bit0 ;
|
w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
|
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
|
w_reg_select_dec = 56'h00_0000_0100_0000 ; // The same for another address
|
end
|
end
|
`P_AM5_ADDR: // w_reg_select_dec bit 25
|
`P_AM5_ADDR: // w_reg_select_dec bit 25
|
begin
|
begin
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
|
| Line 1515... |
Line 1518... |
pci_img_ctrl5_bit2_1 <= 2'h0 ;
|
pci_img_ctrl5_bit2_1 <= 2'h0 ;
|
pci_ba5_bit31_12 <= 20'h0000_0 ;
|
pci_ba5_bit31_12 <= 20'h0000_0 ;
|
`ifdef HOST
|
`ifdef HOST
|
pci_ba5_bit0 <= `PCI_BA5_MEM_IO ;
|
pci_ba5_bit0 <= `PCI_BA5_MEM_IO ;
|
`endif
|
`endif
|
pci_am5 <= `PCI_AM0;
|
pci_am5 <= `PCI_AM5;
|
pci_ta5 <= 20'h0000_0 ;
|
pci_ta5 <= 20'h0000_0 ;
|
`endif
|
`endif
|
/*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
|
/*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
|
/*pci_err_addr ;*/
|
/*pci_err_addr ;*/
|
/*pci_err_data ;*/
|
/*pci_err_data ;*/
|
| Line 3345... |
Line 3348... |
assign icr_soft_res = icr_bit31 ;
|
assign icr_soft_res = icr_bit31 ;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
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|
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|
|
|
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|
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|
