URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [decoder.v] - Diff between revs 6 and 21

Rev 6	Rev 21
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2001/10/05 08:14:28 mihad`
	`// Updated all files with inclusion of timescale file for simulation purposes.`
	`//`
`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
`// New project directory structure`	`// New project directory structure`
`//`	`//`
`//`	`//`

`include "constants.v"	`include "pci_constants.v"

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`

`module DECODER (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en) ;`	`module DECODER (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en) ;`

`// Decoding address size parameter - for FPGAs 1MegByte is recommended`	`// Decoding address size parameter - for FPGAs 1MegByte is recommended`
`// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!`	`// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!`