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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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Line 427... |
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// clocks counter - it counts how many clock cycles completion is present without beeing repeated
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// clocks counter - it counts how many clock cycles completion is present without beeing repeated
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// if it counts to 2^^16 cycles the completion must be ditched
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// if it counts to 2^^16 cycles the completion must be ditched
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// wire for clearing this counter
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// wire for clearing this counter
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wire clear_count = in_progress_in || ~req_comp_pending_out ;
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wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
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always@(posedge req_clk_in or posedge reset_in)
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always@(posedge req_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
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comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
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else
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else
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