| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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| Line 65... |
Line 68... |
wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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flush_in,
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flush_in,
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almost_full_out,
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full_out,
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full_out,
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almost_empty_out,
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almost_empty_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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| Line 91... |
Line 93... |
input reset_in;
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input reset_in;
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// flush input
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// flush input
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input flush_in ;
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input flush_in ;
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// almost full and empy status outputs
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// almost empy status output
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output almost_full_out, almost_empty_out;
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output almost_empty_out;
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// full and empty status outputs
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// full and empty status outputs
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output full_out, empty_out;
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output full_out, empty_out;
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// read and write addresses outputs
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// read and write addresses outputs
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| Line 120... |
Line 122... |
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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| Line 132... |
Line 133... |
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// FFs for registered empty and full flags
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// FFs for registered empty and full flags
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reg empty ;
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reg empty ;
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reg full ;
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reg full ;
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// almost_empty and almost_full tag - implemented as latches
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// almost_empty tag
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reg almost_empty ;
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reg almost_empty ;
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reg almost_full ;
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// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && ~full ;
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wire wallow = wenable_in && ~full ;
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// write allow output assignment
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// write allow output assignment
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| Line 148... |
Line 148... |
wire rallow ;
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wire rallow ;
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// full output assignment
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// full output assignment
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assign full_out = full ;
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assign full_out = full ;
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// almost full output assignment
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assign almost_full_out = almost_full && ~full ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in || flush_in ;
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wire clear = reset_in || flush_in ;
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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always@(posedge reset_in or posedge wclock_in)
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always@(posedge reset_in or posedge wclock_in)
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| Line 197... |
Line 194... |
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 5 - one more than initial value of read address
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// initial value is 4 - one more than initial value of read address
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr_plus_one <= #`FF_DELAY 4 ;
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end
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end
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else if (rallow)
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else if (rallow)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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end
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 4
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// initial value is 3
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raddr <= #`FF_DELAY 4 ;
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raddr <= #`FF_DELAY 3 ;
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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/*-----------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------
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Read address control consists of Read address counter and Grey Address pipeline
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Read address control consists of Read address counter and Grey Address pipeline
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There are 4 Grey addresses:
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There are 4 Grey addresses:
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- rgrey_minus2 is Grey Code of address two before current address
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- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_addr is Grey Code of current read address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
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- rgrey_next is Grey Code of next read address
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--------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------*/
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// grey code register for two before read address
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always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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begin
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// initial value is 0
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rgrey_minus2 <= #`FF_DELAY 0 ;
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end
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else
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if (rallow)
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rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
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end
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// grey code register for one before read address
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// grey code register for one before read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 1
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// initial value is 0
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rgrey_minus1 <= #`FF_DELAY 1 ;
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rgrey_minus1 <= #`FF_DELAY 0 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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end
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end
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| Line 253... |
Line 237... |
// grey code register for read address - represents current Read Address
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// grey code register for read address - represents current Read Address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 3
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// initial value is 1
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rgrey_addr <= #`FF_DELAY 3 ;
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rgrey_addr <= #`FF_DELAY 1 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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end
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end
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| Line 266... |
Line 250... |
// grey code register for next read address - represents Grey Code of next read address
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// grey code register for next read address - represents Grey Code of next read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 2
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// initial value is 3
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rgrey_next <= #`FF_DELAY 2 ;
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rgrey_next <= #`FF_DELAY 3 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow)
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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| Line 285... |
Line 269... |
// grey code register for one before write address
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// grey code register for one before write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 1
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// initial value is 0
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wgrey_minus1 <= #`FF_DELAY 1 ;
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wgrey_minus1 <= #`FF_DELAY 0 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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end
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end
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| Line 298... |
Line 282... |
// grey code register for write address
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// grey code register for write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 3
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// initial value is 1
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wgrey_addr <= #`FF_DELAY 3 ;
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wgrey_addr <= #`FF_DELAY 1 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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end
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end
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| Line 311... |
Line 295... |
// grey code register for next write address
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// grey code register for next write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 2
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// initial value is 3
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wgrey_next <= #`FF_DELAY 2 ;
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wgrey_next <= #`FF_DELAY 3 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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// write address counter - nothing special except initial value
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// write address counter - nothing special except initial value
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value 4
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// initial value 3
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waddr <= #`FF_DELAY 4 ;
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waddr <= #`FF_DELAY 3 ;
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else
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else
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if (wallow)
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if (wallow)
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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end
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end
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| Line 340... |
Line 324... |
Registered almost full control:
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Registered almost full control:
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Almost full flag is set on rising write clock edge whenever two free locations are left in fifo and another entry is written to it.
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Almost full flag is set on rising write clock edge whenever two free locations are left in fifo and another entry is written to it.
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It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
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It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire comb_full = wgrey_next == rgrey_addr ;
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wire comb_full = wgrey_next == rgrey_addr ;
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wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
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wire comb_almost_full = wgrey_next == rgrey_minus1 ;
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wire comb_two_left = wgrey_next == rgrey_minus2 ;
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//combinatorial input to Registered full FlipFlop
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//combinatorial input to Registered full FlipFlop
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wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
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wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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| Line 354... |
Line 337... |
full <= #`FF_DELAY 1'b0 ;
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full <= #`FF_DELAY 1'b0 ;
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else
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else
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full <= #`FF_DELAY reg_full ;
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full <= #`FF_DELAY reg_full ;
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end
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end
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// input for almost full flip flop
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wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
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always@(posedge clear or posedge wclock_in)
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begin
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if (clear)
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almost_full <= #`FF_DELAY 1'b0 ;
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else
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almost_full <= #`FF_DELAY reg_almost_full_in ;
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end
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Registered empty control:
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Registered empty control:
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registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
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registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
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something is written to fifo which is detected on next read clock edge.
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something is written to fifo which is detected on next read clock edge.
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