URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [fifo_control.v] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
	`// New project directory structure`
	`//`
`//`	`//`

`/* FIFO_CONTROL module provides read/write address and status generation for`	`/* FIFO_CONTROL module provides read/write address and status generation for`
`FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */`	`FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */`

Line 53...	Line 56...
`ifdef SYNCHRONOUS	`ifdef SYNCHRONOUS
`else	`else
`define SYNCHRONOUS	`define SYNCHRONOUS
`endif	`endif
`endif	`endif

	`include "timescale.v"

`module FIFO_CONTROL`	`module FIFO_CONTROL`
`(`	`(`
`rclock_in,`	`rclock_in,`
`wclock_in,`	`wclock_in,`
`renable_in,`	`renable_in,`