| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/10/05 08:14:28 mihad
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
|
//
|
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
|
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
|
// New project directory structure
|
// New project directory structure
|
//
|
//
|
//
|
//
|
|
|
`include "constants.v"
|
`include "pci_constants.v"
|
|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
|
|
// module inferes a single IOB output block as known in FPGA architectures
|
// module inferes a single IOB output block as known in FPGA architectures
|
// It provides data flip flop with clock enable and output enable flip flop with clock enable
|
// It provides data flip flop with clock enable and output enable flip flop with clock enable
|
// This is tested in Xilinx FPGA - active low output enable
|
// This is tested in Xilinx FPGA - active low output enable
|
// Check polarity of output enable flip flop for specific architecure.
|
// Check polarity of output enable flip flop for specific architecure.
|
| Line 77... |
Line 83... |
output en_out ;
|
output en_out ;
|
|
|
reg dat_out,
|
reg dat_out,
|
en_out ;
|
en_out ;
|
|
|
wire en_n = ~en_in ;
|
`ifdef ACTIVE_LOW_OE
|
|
wire en = ~en_in ;
|
|
`else
|
|
`ifdef ACTIVE_HIGH_OE
|
|
wire en = en_in ;
|
|
`endif
|
|
`endif
|
|
|
always@(posedge reset_in or posedge clk_in)
|
always@(posedge reset_in or posedge clk_in)
|
begin
|
begin
|
if ( reset_in )
|
if ( reset_in )
|
dat_out <= #`FF_DELAY 1'b0 ;
|
dat_out <= #`FF_DELAY 1'b0 ;
|
| Line 90... |
Line 102... |
end
|
end
|
|
|
always@(posedge reset_in or posedge clk_in)
|
always@(posedge reset_in or posedge clk_in)
|
begin
|
begin
|
if ( reset_in )
|
if ( reset_in )
|
|
`ifdef ACTIVE_LOW_OE
|
en_out <= #`FF_DELAY 1'b1 ;
|
en_out <= #`FF_DELAY 1'b1 ;
|
|
`else
|
|
`ifdef ACTIVE_HIGH_OE
|
|
en_out <= #`FF_DELAY 1'b0 ;
|
|
`endif
|
|
`endif
|
else if ( en_en_in )
|
else if ( en_en_in )
|
en_out <= #`FF_DELAY en_n ;
|
en_out <= #`FF_DELAY en ;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
