URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [out_reg.v] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 40...	Line 40...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
	`// New project directory structure`
	`//`
`//`	`//`

`include "constants.v"	`include "constants.v"
	`include "timescale.v"

`// module inferes a single IOB output block as known in FPGA architectures`	`// module inferes a single IOB output block as known in FPGA architectures`
`// It provides data flip flop with clock enable and output enable flip flop with clock enable`	`// It provides data flip flop with clock enable and output enable flip flop with clock enable`
`// This is tested in Xilinx FPGA - active low output enable`	`// This is tested in Xilinx FPGA - active low output enable`
`// Check polarity of output enable flip flop for specific architecure.`	`// Check polarity of output enable flip flop for specific architecure.`