| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/17 22:51:50 tadejm
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// Changed BIST signals for RAMs.
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//
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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//
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//
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// Revision 1.4 2002/10/08 17:17:05 mihad
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// Revision 1.4 2002/10/08 17:17:05 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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| Line 171... |
Line 174... |
// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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scanb_rst, // bist scan reset
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scanb_clk, // bist scan clock
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scanb_clk, // bist scan clock
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scanb_si, // bist scan serial in
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scanb_si, // bist scan serial in
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scanb_so, // bist scan serial out
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scanb_so, // bist scan serial out
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scanb_sen // bist scan shift enable
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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// WISHBONE system signals
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// WISHBONE system signals
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input CLK_I ;
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input CLK_I ;
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| Line 277... |
Line 280... |
-----------------------------------------------------*/
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-----------------------------------------------------*/
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input scanb_rst; // bist scan reset
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input scanb_rst; // bist scan reset
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input scanb_clk; // bist scan clock
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input scanb_clk; // bist scan clock
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input scanb_si; // bist scan serial in
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input scanb_si; // bist scan serial in
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output scanb_so; // bist scan serial out
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output scanb_so; // bist scan serial out
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input scanb_sen; // bist scan shift enable
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input scanb_en; // bist scan shift enable
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// internal wires for serial chain connection
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// internal wires for serial chain connection
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wire SO_internal ;
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wire SO_internal ;
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wire SI_internal = SO_internal ;
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wire SI_internal = SO_internal ;
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`endif
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`endif
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| Line 801... |
Line 804... |
,
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,
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so),
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.scanb_sen (scanb_sen)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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// PCI TARGET UNIT INPUTS
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// PCI TARGET UNIT INPUTS
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wire [31:0] pciu_mdata_in = MDAT_I ;
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wire [31:0] pciu_mdata_in = MDAT_I ;
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| Line 983... |
Line 986... |
,
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,
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so),
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.scanb_sen (scanb_sen)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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// CONFIGURATION SPACE INPUTS
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// CONFIGURATION SPACE INPUTS
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