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https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_bridge32.v] - Diff between revs 68 and 69
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| Rev 68 |
Rev 69 |
| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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//
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// Revision 1.6 2002/10/17 22:51:50 tadejm
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// Revision 1.6 2002/10/17 22:51:50 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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| Line 803... |
Line 806... |
`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so_internal),
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.scanb_en (scanb_en)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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// PCI TARGET UNIT INPUTS
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// PCI TARGET UNIT INPUTS
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| Line 984... |
Line 987... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_so_internal),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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