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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_decoder.v] - Diff between revs 2 and 6

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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
 
// New project directory structure
 
//
//
//
 
 
`include "constants.v"
`include "constants.v"
 
`include "timescale.v"
 
 
module PCI_DECODER (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en, mem_io_space, mem_en, io_en) ;
module PCI_DECODER (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en, mem_io_space, mem_en, io_en) ;
 
 
// Decoding address size parameter - for FPGAs 1MegByte is recommended
// Decoding address size parameter - for FPGAs 1MegByte is recommended
//   MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!
//   MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!

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