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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// this module instantiates output flip flops for PCI interface and
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// this module instantiates output flip flops for PCI interface and
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// some fanout downsizing logic because of heavily constrained PCI signals
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// some fanout downsizing logic because of heavily constrained PCI signals
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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module PCI_IO_MUX
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module PCI_IO_MUX
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(
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(
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reset_in,
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reset_in,
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clk_in,
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clk_in,
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| Line 66... |
Line 71... |
trdy_in,
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trdy_in,
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trdy_en_in,
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trdy_en_in,
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stop_in,
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stop_in,
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stop_en_in,
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stop_en_in,
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master_load_in,
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master_load_in,
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master_load_on_transfer_in,
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target_load_in,
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target_load_in,
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target_load_on_transfer_in,
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cbe_in,
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cbe_in,
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cbe_en_in,
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cbe_en_in,
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mas_ad_in,
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mas_ad_in,
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tar_ad_in,
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tar_ad_in,
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| Line 100... |
Line 107... |
devsel_out,
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devsel_out,
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trdy_out,
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trdy_out,
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stop_out,
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stop_out,
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cbe_out,
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cbe_out,
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ad_out,
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ad_out,
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ad_load_out,
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ad_en_unregistered_out,
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par_out,
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par_out,
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par_en_out,
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par_en_out,
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perr_out,
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perr_out,
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perr_en_out,
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perr_en_out,
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serr_out,
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serr_out,
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serr_en_out,
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serr_en_out,
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req_out,
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req_out,
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req_en_out
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req_en_out,
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pci_trdy_in,
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pci_irdy_in,
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pci_frame_in,
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pci_stop_in
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);
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);
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input reset_in, clk_in ;
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input reset_in, clk_in ;
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input frame_in ;
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input frame_in ;
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Line 172... |
output devsel_out ;
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output devsel_out ;
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output trdy_out ;
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output trdy_out ;
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output stop_out ;
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output stop_out ;
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output [3:0] cbe_out ;
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output [3:0] cbe_out ;
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output [31:0] ad_out ;
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output [31:0] ad_out ;
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output ad_load_out ;
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output ad_en_unregistered_out ;
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output par_out ;
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output par_out ;
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output par_en_out ;
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output par_en_out ;
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output perr_out ;
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output perr_out ;
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output perr_en_out ;
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output perr_en_out ;
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Line 187... |
input req_in ;
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input req_in ;
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output req_out ;
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output req_out ;
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output req_en_out ;
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output req_en_out ;
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input pci_trdy_in,
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pci_irdy_in,
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pci_frame_in,
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pci_stop_in ;
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input master_load_on_transfer_in ;
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input target_load_on_transfer_in ;
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wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
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wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
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wire ad_en_ctrl_low ;
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wire ad_en_ctrl_low ;
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IO_MUX_EN_MULT ad_en_low_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_low)) ;
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wire ad_en_ctrl_mlow ;
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wire ad_en_ctrl_mlow ;
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IO_MUX_EN_MULT ad_en_mlow_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mlow)) ;
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wire ad_en_ctrl_mhigh ;
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wire ad_en_ctrl_mhigh ;
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IO_MUX_EN_MULT ad_en_mhigh_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mhigh)) ;
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wire ad_en_ctrl_high ;
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wire ad_en_ctrl_high ;
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IO_MUX_EN_MULT ad_en_high_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_high)) ;
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wire ad_load_ctrl_low ;
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wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
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IO_MUX_LOAD_MUX ad_load_low_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_low));
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wire ad_load_ctrl_mlow ;
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PCI_IO_MUX_AD_EN_CRIT ad_en_low_gen
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IO_MUX_LOAD_MUX ad_load_mlow_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mlow));
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_low)
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);
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wire ad_load_ctrl_mhigh ;
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PCI_IO_MUX_AD_EN_CRIT ad_en_mlow_gen
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IO_MUX_LOAD_MUX ad_load_mhigh_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mhigh));
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_mlow)
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);
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PCI_IO_MUX_AD_EN_CRIT ad_en_mhigh_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_mhigh)
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);
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PCI_IO_MUX_AD_EN_CRIT ad_en_high_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_high)
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);
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assign ad_en_unregistered_out = ad_en_ctrl_high ;
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wire load = master_load_in || target_load_in ;
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wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
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wire ad_load_ctrl_low ;
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wire ad_load_ctrl_mlow ;
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wire ad_load_ctrl_mhigh ;
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wire ad_load_ctrl_high ;
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wire ad_load_ctrl_high ;
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IO_MUX_LOAD_MUX ad_load_high_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_high)) ;
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assign ad_load_out = ad_load_ctrl_high ;
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PCI_IO_MUX_AD_LOAD_CRIT ad_load_low_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_low)
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);
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PCI_IO_MUX_AD_LOAD_CRIT ad_load_mlow_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_mlow)
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);
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PCI_IO_MUX_AD_LOAD_CRIT ad_load_mhigh_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_mhigh)
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);
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PCI_IO_MUX_AD_LOAD_CRIT ad_load_high_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_high)
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);
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OUT_REG ad_iob0
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OUT_REG ad_iob0
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(
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(
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.reset_in ( reset_in ),
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.clk_in ( clk_in) ,
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