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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`include "constants.v"
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`include "pci_constants.v"
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`include "bus_commands.v"
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`include "bus_commands.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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/*====================================================================
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/*====================================================================
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Module provides interface between PCI bridge internals and PCI master
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Module provides interface between PCI bridge internals and PCI master
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state machine
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state machine
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====================================================================*/
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====================================================================*/
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| Line 77... |
Line 83... |
// status inputs from master SM
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// status inputs from master SM
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wait_in,
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wait_in,
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wtransfer_in,
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wtransfer_in,
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rtransfer_in,
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rtransfer_in,
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retry_in,
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retry_in,
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werror_in,
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rerror_in,
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rerror_in,
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first_in ,
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first_in ,
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mabort_in,
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mabort_in,
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| Line 115... |
Line 120... |
// error reporting
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// error reporting
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err_addr_out,
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err_addr_out,
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err_bc_out,
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err_bc_out,
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err_signal_out,
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err_signal_out,
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err_source_out,
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err_source_out,
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err_pending_in,
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err_rty_exp_out,
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err_rty_exp_out,
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cache_line_size_in,
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cache_line_size_in,
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// two signals for pci control and status
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// two signals for pci control and status
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mabort_received_out,
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mabort_received_out,
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tabort_received_out
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tabort_received_out,
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posted_write_not_present_out
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);
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);
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// system inputs
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// system inputs
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input clk_in ;
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input clk_in ;
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input reset_in ;
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input reset_in ;
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| Line 157... |
Line 163... |
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input wait_in,
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input wait_in,
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wtransfer_in,
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wtransfer_in,
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rtransfer_in,
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rtransfer_in,
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retry_in,
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retry_in,
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werror_in,
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rerror_in,
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rerror_in,
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first_in ,
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first_in ,
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mabort_in ;
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mabort_in ;
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// WISHBONE write fifo interconnect
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// WISHBONE write fifo interconnect
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| Line 202... |
Line 207... |
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output err_signal_out ; // error signalization
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output err_signal_out ; // error signalization
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output err_source_out ; // error source indicator
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output err_source_out ; // error source indicator
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input err_pending_in ;
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input [7:0] cache_line_size_in ; // cache line size value input
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input [7:0] cache_line_size_in ; // cache line size value input
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output err_rty_exp_out ; // retry expired error output
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output err_rty_exp_out ; // retry expired error output
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output mabort_received_out ; // master abort signaled to status register
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output mabort_received_out ; // master abort signaled to status register
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output tabort_received_out ; // target abort signaled to status register
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output tabort_received_out ; // target abort signaled to status register
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output posted_write_not_present_out ; // used in target state machine - must deny read completions when this signal is 0
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assign err_bc_out = bc_out ;
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assign err_bc_out = bc_out ;
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// assign read outputs
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// assign read outputs
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/*==================================================================================================================
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/*==================================================================================================================
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| Line 255... |
Line 260... |
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// error recovery indicator
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// error recovery indicator
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reg err_recovery ;
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reg err_recovery ;
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// operation is locked until error recovery is in progress or error bit is not cleared in configuration space
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// operation is locked until error recovery is in progress or error bit is not cleared in configuration space
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wire err_lock = err_recovery || err_pending_in ;
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wire err_lock = err_recovery ;
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// three requests are possible - posted write, delayed write and delayed read
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// three requests are possible - posted write, delayed write and delayed read
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reg del_write_req ;
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reg del_write_req ;
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reg posted_write_req ;
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reg posted_write_req ;
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reg del_read_req ;
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reg del_read_req ;
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// assign request output
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// assign request output
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assign req_out = del_write_req || posted_write_req || del_read_req ;
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assign req_out = del_write_req || posted_write_req || del_read_req ;
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// posted write is not present, when WB Write Fifo is empty and posted write transaction is not beeing requested at present time
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assign posted_write_not_present_out = !posted_write_req && wbw_fifo_empty_in ;
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// write requests are staged, so data is read from source into current data register and next data register
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// write requests are staged, so data is read from source into current data register and next data register
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reg write_req_int ;
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reg write_req_int ;
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if ( reset_in )
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if ( reset_in )
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| Line 315... |
Line 323... |
end
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end
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// multiplexer for data output to PCI MASTER state machine
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// multiplexer for data output to PCI MASTER state machine
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reg [31:0] source_data ;
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reg [31:0] source_data ;
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reg [3:0] source_be ;
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reg [3:0] source_be ;
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always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in)
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always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in or del_burst_in)
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begin
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begin
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case (data_source)
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case (data_source)
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POSTED_WRITE: begin
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POSTED_WRITE: begin
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source_data = wbw_fifo_addr_data_in ;
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source_data = wbw_fifo_addr_data_in ;
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source_be = wbw_fifo_cbe_in ;
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source_be = wbw_fifo_cbe_in ;
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end
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end
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DELAYED_WRITE: begin
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DELAYED_WRITE: begin
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source_data = del_wdata_in ;
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source_data = del_wdata_in ;
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source_be = ~del_be_in ;
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// read all bytes during delayed burst read!
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source_be = ~( del_be_in | {4{del_burst_in}} ) ;
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end
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end
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endcase
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endcase
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end
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end
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wire waddr = wbw_fifo_control_in[`ADDR_CTRL_BIT] ;
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wire waddr = wbw_fifo_control_in[`ADDR_CTRL_BIT] ;
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| Line 340... |
Line 349... |
// load address and bus command from wbw_fifo, else load data from delayed transaction logic
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// load address and bus command from wbw_fifo, else load data from delayed transaction logic
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wire [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ;
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wire [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ;
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wire [3:0] new_bc = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ;
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wire [3:0] new_bc = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ;
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// address counter enable - only for posted writes when data is actually transfered
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// address counter enable - only for posted writes when data is actually transfered
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wire addr_count_en = ~wait_in && posted_write_req && wtransfer_in ;
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wire addr_count_en = ~wait_in && posted_write_req && rtransfer_in ;
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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bc_out <= #`FF_DELAY `BC_RESERVED0 ;
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bc_out <= #`FF_DELAY `BC_RESERVED0 ;
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else
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else
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if (address_change)
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if (address_change)
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bc_out <= #`FF_DELAY new_bc ;
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bc_out <= #`FF_DELAY new_bc ;
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end
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end
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reg [31:2] current_dword_address ;
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reg [29:0] current_dword_address ;
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// DWORD address counter with load
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// DWORD address counter with load
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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| Line 389... |
Line 398... |
wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in ;
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wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in ;
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// cache line counter is loaded when del read request is not in progress
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// cache line counter is loaded when del read request is not in progress
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wire read_count_load = ~del_read_req ;
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wire read_count_load = ~del_read_req ;
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reg [8:0] max_read_count ;
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reg [(`WBR_ADDR_LENGTH - 1):0] max_read_count ;
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always@(cache_line_size_in or del_bc_in)
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always@(cache_line_size_in or del_bc_in)
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begin
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begin
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if ( (cache_line_size_in >= `WBR_DEPTH) || (~del_bc_in[1] && ~del_bc_in[0]) )
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if ( (cache_line_size_in >= `WBR_DEPTH) || (~del_bc_in[1] && ~del_bc_in[0]) )
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max_read_count = `WBR_DEPTH - 1'b1;
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max_read_count = `WBR_DEPTH - 1'b1;
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else
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else
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max_read_count = cache_line_size_in ;
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max_read_count = cache_line_size_in ;
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end
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end
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reg [8:0] read_count ;
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reg [(`WBR_ADDR_LENGTH - 1):0] read_count ;
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// cache line bound indicator - it signals when data for one complete cacheline was read
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// cache line bound indicator - it signals when data for one complete cacheline was read
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wire read_bound_comb = ~|(read_count[8:2]) ;
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wire read_bound_comb = ~|(read_count[(`WBR_ADDR_LENGTH - 1):2]) ;
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reg read_bound ;
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reg read_bound ;
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always@(posedge clk_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if (read_count_load)
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if ( reset_in )
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read_bound <= #`FF_DELAY 1'b0 ;
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else if (read_count_load)
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read_bound <= #`FF_DELAY 1'b0 ;
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read_bound <= #`FF_DELAY 1'b0 ;
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else if ( read_count_enable )
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else if ( read_count_enable )
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read_bound <= #`FF_DELAY read_bound_comb ;
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read_bound <= #`FF_DELAY read_bound_comb ;
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end
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end
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// down counter with load
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// down counter with load
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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read_count <= #`FF_DELAY 8'h00 ;
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read_count <= #`FF_DELAY 0 ;
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else
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else
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if (read_count_load)
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if (read_count_load)
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read_count <= #`FF_DELAY max_read_count ;
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read_count <= #`FF_DELAY max_read_count ;
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else
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else
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if (read_count_enable)
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if (read_count_enable)
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| Line 705... |
Line 716... |
wire del_write_complete = del_write_req && ( rtransfer_in || rerror_in || mabort_in ) ;
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wire del_write_complete = del_write_req && ( rtransfer_in || rerror_in || mabort_in ) ;
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wire del_read_complete = del_read_req && ( rerror_in || mabort_in || ( last_transfered ) || ( retry_in && ~first_in ) ) ;
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wire del_read_complete = del_read_req && ( rerror_in || mabort_in || ( last_transfered ) || ( retry_in && ~first_in ) ) ;
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assign del_complete_out = ~wait_in && ( del_write_complete || del_read_complete ) ;
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assign del_complete_out = ~wait_in && ( del_write_complete || del_read_complete ) ;
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// next last output generation
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// next last output generation
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assign next_last_out = del_write_req || del_read_req && ( ~del_burst_in || read_bound ) || posted_write_req && ( write_next_last ) ;
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assign next_last_out = del_write_req || del_read_req && ( ~del_burst_in || read_bound ) || posted_write_req && ( write_next_last ) ;
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/*==================================================================================================================
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/*==================================================================================================================
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Error recovery FF gets a value of one, when during posted write error occurs. It is cleared when all the data provided
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Error recovery FF gets a value of one, when during posted write error occurs. It is cleared when all the data provided
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for erroneous transaction is pulled out of WBW_FIFO
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for erroneous transaction is pulled out of WBW_FIFO
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| Line 730... |
Line 740... |
else
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else
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// when error recovery is set, wbw_fifo is enabled - clear err_recovery when last data entry of erroneous transaction is pulled out of fifo
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// when error recovery is set, wbw_fifo is enabled - clear err_recovery when last data entry of erroneous transaction is pulled out of fifo
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err_recovery_in = ~wlast ;
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err_recovery_in = ~wlast ;
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end
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end
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wire data_load_slow = (req_out && ~rdy_out) && (del_read_req || write_req_int) ;
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wire data_out_load = (posted_write_req || del_write_req) && ( !rdy_out || ( !wait_in && rtransfer_in ) ) ;
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wire data_load_en = posted_write_req && ~last_out && ~wait_in ;
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wire data_be_load = data_load_slow || (data_load_en && wtransfer_in) ;
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wire be_out_load = (req_out && !rdy_out) || ( posted_write_req && !wait_in && rtransfer_in ) ;
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wire last_load = req_out && ( ~rdy_out || ~wait_in && wtransfer_in ) ;
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wire last_load = req_out && ( ~rdy_out || ~wait_in && wtransfer_in ) ;
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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begin
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be_out <= #`FF_DELAY 4'hF ;
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data_out <= #`FF_DELAY 32'h0000_0000 ;
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data_out <= #`FF_DELAY 32'h0000_0000 ;
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end
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else
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else
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if ( data_be_load )
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if ( data_out_load )
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begin
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data_out <= #`FF_DELAY intermediate_data ;
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data_out <= #`FF_DELAY next_data_out ;
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be_out <= #`FF_DELAY next_be_out ;
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end
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end
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always@(posedge clk_in or posedge reset_in)
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begin
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if ( reset_in )
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be_out <= #`FF_DELAY 4'hF ;
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else
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if ( be_out_load )
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be_out <= #`FF_DELAY posted_write_req ? intermediate_be : source_be ;
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end
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end
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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| Line 762... |
Line 775... |
current_last <= #`FF_DELAY next_last_out ;
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current_last <= #`FF_DELAY next_last_out ;
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end
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end
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assign last_out = current_last ;
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assign last_out = current_last ;
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endmodule
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endmodule
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