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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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module PCI_TARGET32_CLK_EN
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module PCI_TARGET32_CLK_EN
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(
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(
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addr_phase,
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addr_phase,
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config_access,
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config_access,
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addr_claim_in,
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addr_claim_in,
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disconect_wo_data_in,
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pcir_fifo_data_err_in,
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rw_cbe0,
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pci_frame_in,
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pci_frame_in,
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pci_irdy_in,
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state_wait,
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state_wait,
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state_transfere,
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state_transfere,
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state_backoff,
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state_default,
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state_default,
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clk_enable
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clk_enable
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);
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);
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input addr_phase ; // indicates registered address phase on PCI bus
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input addr_phase ; // indicates registered address phase on PCI bus
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input config_access ; // indicates configuration access
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input config_access ; // indicates configuration access
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input addr_claim_in ; // indicates claimed input PCI address
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input addr_claim_in ; // indicates claimed input PCI address
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input disconect_wo_data_in ; // indicates disconnect without data termination from backend
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input pcir_fifo_data_err_in ; // indicates FIFO data error termination from backend
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input rw_cbe0 ; // registered (through all cycle) RW (CBE[0]) input signal from PCI bus
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input pci_frame_in ; // critical constrained input signal
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input pci_frame_in ; // critical constrained input signal
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input pci_irdy_in ; // critical constrained input signal
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input state_wait ; // indicates WAIT state of FSM
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input state_wait ; // indicates WAIT state of FSM
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input state_transfere ; // indicates TRANSFERE state of FSM
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input state_transfere ; // indicates TRANSFERE state of FSM
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input state_backoff ; // indicates BACKOFF state of FSM
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input state_default ; // indicates DEFAULT state of FSM
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input state_default ; // indicates DEFAULT state of FSM
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output clk_enable ; // FSM clock enable output
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output clk_enable ; // FSM clock enable output
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// clock enable signal when FSM is in WAIT state or in DEFAULT state
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// clock enable signal when FSM is in WAIT state or in DEFAULT state
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wire s_wait_clk_en = (state_wait || state_default) ;
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wire s_wait_clk_en = (state_wait || state_default) ;
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// clock enable signal when FSM is in TRANSFERE state
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// clock enable signal when FSM is in TRANSFERE state
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wire s_tran_clk_en = state_transfere &&
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wire s_tran_clk_en = (state_transfere && pci_frame_in) ;
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((disconect_wo_data_in && ~pci_irdy_in && ~pci_frame_in) || (pci_frame_in) ||
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(~rw_cbe0 && pcir_fifo_data_err_in && ~pci_irdy_in && ~pci_frame_in)) ;
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// clock enable signal when FSM is in BACKOFF state
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wire s_bcko_clk_en = (state_backoff && pci_frame_in) ;
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// Clock enable signal for FSM with preserved hierarchy for minimum delay!
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// Clock enable signal for FSM with preserved hierarchy for minimum delay!
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assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en || s_bcko_clk_en) ;
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assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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