| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
|
//
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
// New project directory structure
|
// New project directory structure
|
//
|
//
|
//
|
//
|
|
|
`define FSM_BITS 2 // number of bits needed for FSM states
|
`define P_FSM_BITS 2 // number of bits needed for FSM states
|
|
|
|
`include "pci_constants.v"
|
|
|
`include "bus_commands.v"
|
// synopsys translate_off
|
`include "constants.v"
|
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
|
|
module PCI_TARGET32_SM
|
module PCI_TARGET32_SM
|
(
|
(
|
// system inputs
|
// system inputs
|
clk_in,
|
clk_in,
|
| Line 71... |
Line 75... |
pci_stop_out,
|
pci_stop_out,
|
pci_devsel_out,
|
pci_devsel_out,
|
pci_trdy_en_out,
|
pci_trdy_en_out,
|
pci_stop_en_out,
|
pci_stop_en_out,
|
pci_devsel_en_out,
|
pci_devsel_en_out,
|
pci_target_load_out,
|
ad_load_out,
|
|
ad_load_on_transfer_out,
|
// address, data, bus command, byte enable in/outs
|
// address, data, bus command, byte enable in/outs
|
pci_ad_reg_in,
|
pci_ad_reg_in,
|
pci_ad_out,
|
pci_ad_out,
|
pci_ad_en_out,
|
pci_ad_en_out,
|
pci_cbe_reg_in,
|
pci_cbe_reg_in,
|
bckp_trdy_en_in,
|
bckp_trdy_en_in,
|
bckp_devsel_in,
|
bckp_devsel_in,
|
bckp_trdy_in,
|
bckp_trdy_in,
|
bckp_stop_in,
|
bckp_stop_in,
|
|
pci_trdy_reg_in,
|
|
pci_stop_reg_in,
|
|
|
// backend side of state machine with control signals to pci_io_mux ...
|
// backend side of state machine with control signals to pci_io_mux ...
|
address_out,
|
address_out,
|
addr_claim_in,
|
addr_claim_in,
|
bc_out,
|
bc_out,
|
| Line 93... |
Line 100... |
data_in,
|
data_in,
|
be_out,
|
be_out,
|
req_out,
|
req_out,
|
rdy_out,
|
rdy_out,
|
addr_phase_out,
|
addr_phase_out,
|
|
bckp_devsel_out,
|
bckp_trdy_out,
|
bckp_trdy_out,
|
|
bckp_stop_out,
|
last_reg_out,
|
last_reg_out,
|
frame_reg_out,
|
frame_reg_out,
|
fetch_pcir_fifo_out,
|
fetch_pcir_fifo_out,
|
load_medium_reg_out,
|
load_medium_reg_out,
|
sel_fifo_mreg_out,
|
sel_fifo_mreg_out,
|
| Line 109... |
Line 118... |
norm_access_to_config_in,
|
norm_access_to_config_in,
|
read_completed_in,
|
read_completed_in,
|
read_processing_in,
|
read_processing_in,
|
target_abort_in,
|
target_abort_in,
|
disconect_wo_data_in,
|
disconect_wo_data_in,
|
|
disconect_w_data_in,
|
target_abort_set_out,
|
target_abort_set_out,
|
pciw_fifo_full_in,
|
pciw_fifo_full_in,
|
pcir_fifo_data_err_in,
|
pcir_fifo_data_err_in,
|
wbw_fifo_empty_in,
|
wbw_fifo_empty_in,
|
|
wbu_del_read_comp_pending_in,
|
wbu_frame_en_in
|
wbu_frame_en_in
|
|
|
) ;
|
) ;
|
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------------------------------------------------
|
Various parameters needed for state machine and other stuff
|
Various parameters needed for state machine and other stuff
|
----------------------------------------------------------------------------------------------------------------------*/
|
----------------------------------------------------------------------------------------------------------------------*/
|
parameter S_IDLE = `FSM_BITS'h0 ;
|
parameter S_IDLE = `P_FSM_BITS'h0 ;
|
parameter S_WAIT = `FSM_BITS'h1 ;
|
parameter S_WAIT = `P_FSM_BITS'h1 ;
|
parameter S_TRANSFERE = `FSM_BITS'h2 ;
|
parameter S_TRANSFERE = `P_FSM_BITS'h2 ;
|
parameter S_BACKOFF = `FSM_BITS'h3 ;
|
|
|
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
System inputs.
|
System inputs.
|
==================================================================================================================*/
|
==================================================================================================================*/
|
| Line 153... |
Line 163... |
pci_stop_out,
|
pci_stop_out,
|
pci_devsel_out ;
|
pci_devsel_out ;
|
output pci_trdy_en_out,
|
output pci_trdy_en_out,
|
pci_stop_en_out,
|
pci_stop_en_out,
|
pci_devsel_en_out ;
|
pci_devsel_en_out ;
|
output pci_target_load_out ;
|
output ad_load_out ;
|
|
output ad_load_on_transfer_out ;
|
// address, data, bus command, byte enable in/outs
|
// address, data, bus command, byte enable in/outs
|
input [31:0] pci_ad_reg_in ;
|
input [31:0] pci_ad_reg_in ;
|
output [31:0] pci_ad_out ;
|
output [31:0] pci_ad_out ;
|
output pci_ad_en_out ;
|
output pci_ad_en_out ;
|
input [3:0] pci_cbe_reg_in ;
|
input [3:0] pci_cbe_reg_in ;
|
input bckp_trdy_en_in ;
|
input bckp_trdy_en_in ;
|
input bckp_devsel_in ;
|
input bckp_devsel_in ;
|
input bckp_trdy_in ;
|
input bckp_trdy_in ;
|
input bckp_stop_in ;
|
input bckp_stop_in ;
|
|
input pci_trdy_reg_in ;
|
|
input pci_stop_reg_in ;
|
|
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
Other side of PCI Target state machine
|
Other side of PCI Target state machine
|
==================================================================================================================*/
|
==================================================================================================================*/
|
| Line 181... |
Line 193... |
output [3:0] be_out ; // current dataphase byte enable outputs - registered
|
output [3:0] be_out ; // current dataphase byte enable outputs - registered
|
// Port connection control signals from PCI FSM
|
// Port connection control signals from PCI FSM
|
output req_out ; // Read is requested to WB master
|
output req_out ; // Read is requested to WB master
|
output rdy_out ; // DATA / ADDRESS selection when read or write - registered
|
output rdy_out ; // DATA / ADDRESS selection when read or write - registered
|
output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
|
output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
|
|
output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
|
output bckp_trdy_out ; // TRDY output (which is registered) equivalent
|
output bckp_trdy_out ; // TRDY output (which is registered) equivalent
|
|
output bckp_stop_out ; // STOP output (which is registered) equivalent
|
output last_reg_out ; // Indicates last data phase - registered
|
output last_reg_out ; // Indicates last data phase - registered
|
output frame_reg_out ; // FRAME output signal - registered
|
output frame_reg_out ; // FRAME output signal - registered
|
output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
|
output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
|
output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
|
output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
|
output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
|
output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
|
| Line 201... |
Line 215... |
input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
|
input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
|
input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
|
input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
|
input read_completed_in ; // Indicates that read request is completed on WB side
|
input read_completed_in ; // Indicates that read request is completed on WB side
|
input read_processing_in ; // Indicates that read request is processing on WB side
|
input read_processing_in ; // Indicates that read request is processing on WB side
|
input target_abort_in ; // Indicates target abort termination
|
input target_abort_in ; // Indicates target abort termination
|
input disconect_wo_data_in ; // Indicates disconnect with OR without data termination
|
input disconect_wo_data_in ; // Indicates disconnect without data termination
|
|
input disconect_w_data_in ; // Indicates disconnect with data termination
|
input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
|
input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
|
input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
|
input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
|
input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
|
input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
|
|
input wbu_del_read_comp_pending_in ; // Indicates that WB SÈAVE UNIT has a delayed read pending
|
input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
|
input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
|
// address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
|
// address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
|
output target_abort_set_out ; // Signal used to be set in configuration space registers
|
output target_abort_set_out ; // Signal used to be set in configuration space registers
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
| Line 218... |
Line 234... |
// Delayed frame signal for determining the address phase
|
// Delayed frame signal for determining the address phase
|
reg previous_frame ;
|
reg previous_frame ;
|
// Delayed read completed signal for preparing the data from pcir fifo
|
// Delayed read completed signal for preparing the data from pcir fifo
|
reg read_completed_reg ;
|
reg read_completed_reg ;
|
// Delayed disconnect with/without data for stop loading data to PCIW_FIFO
|
// Delayed disconnect with/without data for stop loading data to PCIW_FIFO
|
reg disconect_wo_data_reg ;
|
//reg disconect_wo_data_reg ;
|
|
|
|
wire config_disconnect ;
|
|
wire disconect_wo_data = disconect_wo_data_in || config_disconnect ;
|
|
wire disconect_w_data = disconect_w_data_in ;
|
// Delayed frame signal for determining the address phase!
|
// Delayed frame signal for determining the address phase!
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
previous_frame <= 1'b1 ;
|
previous_frame <= #`FF_DELAY 1'b1 ;
|
read_completed_reg <= 1'b0 ;
|
read_completed_reg <= #`FF_DELAY 1'b0 ;
|
disconect_wo_data_reg <= 1'b0 ;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
previous_frame <= pci_frame_reg_in ;
|
previous_frame <= #`FF_DELAY pci_frame_reg_in ;
|
read_completed_reg <= read_completed_in ;
|
read_completed_reg <= #`FF_DELAY read_completed_in ;
|
disconect_wo_data_reg <= disconect_wo_data_in ;
|
|
end
|
end
|
end
|
end
|
|
|
// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
|
// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
|
wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
|
wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
// Wire tells when there is configuration (read or write) command with IDSEL signal active
|
|
wire config_access = 1'b0 ;
|
|
// Write and read progresses are used for determining next state
|
|
wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
|
|
(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
|
|
wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ;
|
|
`else
|
|
// Wire tells when there is configuration (read or write) command with IDSEL signal active
|
|
wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
|
|
// Write and read progresses are used for determining next state
|
|
wire write_progress = ( (norm_access_to_config_in) ||
|
|
(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
|
|
(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
|
|
wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
|
|
(read_completed_in && wbw_fifo_empty_in) ) ;
|
|
`endif
|
|
`else
|
// Wire tells when there is configuration (read or write) command with IDSEL signal active
|
// Wire tells when there is configuration (read or write) command with IDSEL signal active
|
wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
|
wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
|
|
// Write and read progresses are used for determining next state
|
|
wire write_progress = ( (norm_access_to_config_in) ||
|
|
(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
|
|
(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
|
|
wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
|
|
(read_completed_in && wbw_fifo_empty_in) ) ;
|
|
`endif
|
|
|
// Signal for loadin data to medium register from pcir fifo when read completed from WB side!
|
// Signal for loading data to medium register from pcir fifo when read completed from WB side!
|
wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
|
wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
|
|
|
// Write and read progresses are used for determining next state
|
|
wire write_progress = (
|
|
(norm_access_to_config_in) || (read_completed_in && ~pciw_fifo_full_in) ||
|
|
(~read_processing_in && ~pciw_fifo_full_in)
|
|
) ;
|
|
wire read_progress = ((~read_completed_in && norm_access_to_config_in) || (read_completed_in && wbw_fifo_empty_in)) ;
|
|
|
|
// Write allowed to PCIW_FIFO
|
// Write allowed to PCIW_FIFO
|
wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in) || (~read_processing_in && ~pciw_fifo_full_in)) ;
|
wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
|
|
(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in)) ;
|
// Read allowed from PCIR_FIFO
|
// Read allowed from PCIR_FIFO
|
wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;
|
wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
// Read request is allowed to be proceed regarding the WB side
|
|
wire read_request = (~read_completed_in && ~read_processing_in) ;
|
|
`else
|
// Read request is allowed to be proceed regarding the WB side
|
// Read request is allowed to be proceed regarding the WB side
|
wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
|
wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
|
|
`endif
|
|
`else
|
|
// Read request is allowed to be proceed regarding the WB side
|
|
wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
|
|
`endif
|
|
|
// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
|
// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
|
reg rw_cbe0 ;
|
reg rw_cbe0 ;
|
reg wr_progress ;
|
reg wr_progress ;
|
reg rd_progress ;
|
reg rd_progress ;
|
reg rd_from_fifo ;
|
reg rd_from_fifo ;
|
reg rd_request ;
|
reg rd_request ;
|
reg wr_to_fifo ;
|
reg wr_to_fifo ;
|
reg norm_access_to_conf_reg ;
|
|
reg same_read_reg ;
|
reg same_read_reg ;
|
reg cnf_progress ;
|
|
reg addr_claim_reg ;
|
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
rw_cbe0 <= 1'b0 ;
|
rw_cbe0 <= #`FF_DELAY 1'b0 ;
|
wr_progress <= 1'b0 ;
|
wr_progress <= #`FF_DELAY 1'b0 ;
|
rd_progress <= 1'b0 ;
|
rd_progress <= #`FF_DELAY 1'b0 ;
|
rd_from_fifo <= 1'b0 ;
|
rd_from_fifo <= #`FF_DELAY 1'b0 ;
|
rd_request <= 1'b0 ;
|
rd_request <= #`FF_DELAY 1'b0 ;
|
wr_to_fifo <= 1'b0 ;
|
wr_to_fifo <= #`FF_DELAY 1'b0 ;
|
norm_access_to_conf_reg <= 1'b0 ;
|
same_read_reg <= #`FF_DELAY 1'b0 ;
|
same_read_reg <= 1'b0 ;
|
end
|
cnf_progress <= 1'b0 ;
|
else
|
addr_claim_reg <= 1'b0 ;
|
begin
|
|
if (addr_phase)
|
|
begin
|
|
rw_cbe0 <= #`FF_DELAY pci_cbe_reg_in[0] ;
|
|
wr_progress <= #`FF_DELAY write_progress ;
|
|
rd_progress <= #`FF_DELAY read_progress ;
|
|
rd_from_fifo <= #`FF_DELAY read_from_fifo ;
|
|
rd_request <= #`FF_DELAY read_request ;
|
|
wr_to_fifo <= #`FF_DELAY write_to_fifo ;
|
|
same_read_reg <= #`FF_DELAY same_read_in ;
|
|
end
|
|
end
|
|
end
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
wire norm_access_to_conf_reg = 1'b0 ;
|
|
wire cnf_progress = 1'b0 ;
|
|
`else
|
|
reg norm_access_to_conf_reg ;
|
|
reg cnf_progress ;
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if (reset_in)
|
|
begin
|
|
norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
|
|
cnf_progress <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (addr_phase)
|
|
begin
|
|
norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
|
|
cnf_progress <= #`FF_DELAY config_access ;
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
`else
|
|
reg norm_access_to_conf_reg ;
|
|
reg cnf_progress ;
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if (reset_in)
|
|
begin
|
|
norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
|
|
cnf_progress <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (addr_phase)
|
if (addr_phase)
|
begin
|
begin
|
rw_cbe0 <= pci_cbe_reg_in[0] ;
|
norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
|
wr_progress <= write_progress ;
|
cnf_progress <= #`FF_DELAY config_access ;
|
rd_progress <= read_progress ;
|
|
rd_from_fifo <= read_from_fifo ;
|
|
rd_request <= read_request ;
|
|
wr_to_fifo <= write_to_fifo ;
|
|
norm_access_to_conf_reg <= norm_access_to_config_in ;
|
|
same_read_reg <= same_read_in ;
|
|
cnf_progress <= config_access ;
|
|
addr_claim_reg <= addr_claim_in ;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
`endif
|
|
|
// Signal used in S_WAIT state to determin next state
|
// Signal used in S_WAIT state to determin next state
|
wire s_wait_progress = (
|
wire s_wait_progress = (
|
(~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && ~pcir_fifo_data_err_in) ||
|
(~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(cnf_progress && ~target_abort_in)
|
(cnf_progress && ~target_abort_in)
|
) ;
|
) ;
|
|
|
// Signal used in S_TRANSFERE state to determin next state
|
// Signal used in S_TRANSFERE state to determin next state
|
wire s_tran_progress = (
|
wire s_tran_progress = (
|
(rw_cbe0 && ~disconect_wo_data_in) ||
|
(rw_cbe0 && !disconect_wo_data) ||
|
(~rw_cbe0 && ~disconect_wo_data_in && ~target_abort_in && ~pcir_fifo_data_err_in)
|
(~rw_cbe0 && !disconect_wo_data && !target_abort_in && !pcir_fifo_data_err_in)
|
) ;
|
) ;
|
|
|
// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
|
// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
|
wire pcit_sm_clk_en ;
|
wire pcit_sm_clk_en ;
|
// FSM states signals indicating the current state
|
// FSM states signals indicating the current state
|
reg state_idle ;
|
reg state_idle ;
|
reg state_wait ;
|
reg state_wait ;
|
reg state_transfere ;
|
reg sm_transfere ;
|
reg state_backoff ;
|
reg backoff ;
|
reg state_default ;
|
reg state_default ;
|
|
wire state_backoff = sm_transfere && backoff ;
|
|
wire state_transfere = sm_transfere && !backoff ;
|
|
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
backoff <= #`FF_DELAY 1'b0 ;
|
|
else if ( state_idle )
|
|
backoff <= #`FF_DELAY 1'b0 ;
|
|
else
|
|
backoff <= #`FF_DELAY (state_wait && !s_wait_progress) ||
|
|
(sm_transfere && !s_tran_progress && !pci_frame_in && !pci_irdy_in) ||
|
|
backoff ;
|
|
end
|
|
assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ;
|
|
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_CLK_EN pci_target_clock_en
|
PCI_TARGET32_CLK_EN pci_target_clock_en
|
(
|
(
|
.addr_phase (addr_phase),
|
.addr_phase (addr_phase),
|
.config_access (config_access),
|
.config_access (config_access),
|
.addr_claim_in (addr_claim_in),
|
.addr_claim_in (addr_claim_in),
|
.disconect_wo_data_in (disconect_wo_data_in),
|
|
.pcir_fifo_data_err_in (pcir_fifo_data_err_in),
|
|
.rw_cbe0 (rw_cbe0),
|
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
|
.state_wait (state_wait),
|
.state_wait (state_wait),
|
.state_transfere (state_transfere),
|
.state_transfere (sm_transfere),
|
.state_backoff (state_backoff),
|
|
.state_default (state_default),
|
.state_default (state_default),
|
.clk_enable (pcit_sm_clk_en)
|
.clk_enable (pcit_sm_clk_en)
|
);
|
);
|
|
|
reg [(`FSM_BITS - 1):0] c_state ; //current state register
|
reg [(`P_FSM_BITS - 1):0] c_state ; //current state register
|
reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
|
reg [(`P_FSM_BITS - 1):0] n_state ; //next state input to current state register
|
|
|
// state machine register control
|
// state machine register control
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in) // reset state machine to S_IDLE state
|
if (reset_in) // reset state machine to S_IDLE state
|
| Line 359... |
Line 453... |
if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
|
if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
|
c_state <= #`FF_DELAY n_state ;
|
c_state <= #`FF_DELAY n_state ;
|
end
|
end
|
|
|
// state machine logic
|
// state machine logic
|
always@(c_state or
|
always@(c_state)
|
s_wait_progress or
|
|
s_tran_progress
|
|
)
|
|
begin
|
begin
|
case (c_state)
|
case (c_state)
|
S_IDLE :
|
S_IDLE :
|
begin
|
begin
|
state_idle <= 1'b1 ;
|
state_idle <= 1'b1 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
sm_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
n_state <= S_WAIT ;
|
n_state <= S_WAIT ;
|
end
|
end
|
S_WAIT :
|
S_WAIT :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b1 ;
|
state_wait <= 1'b1 ;
|
state_transfere <= 1'b0 ;
|
sm_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
if (s_wait_progress)
|
|
n_state <= S_TRANSFERE ;
|
n_state <= S_TRANSFERE ;
|
else
|
|
n_state <= S_BACKOFF ;
|
|
end
|
end
|
S_TRANSFERE :
|
S_TRANSFERE :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b1 ;
|
sm_transfere <= 1'b1 ;
|
state_backoff <= 1'b0 ;
|
|
state_default <= 1'b0 ;
|
|
if (s_tran_progress)
|
|
n_state <= S_IDLE ;
|
|
else
|
|
n_state <= S_BACKOFF ;
|
|
end
|
|
S_BACKOFF :
|
|
begin
|
|
state_idle <= 1'b0 ;
|
|
state_wait <= 1'b0 ;
|
|
state_transfere <= 1'b0 ;
|
|
state_backoff <= 1'b1 ;
|
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
sm_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
|
state_default <= 1'b1 ;
|
state_default <= 1'b1 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// if not retry and not target abort
|
// if not retry and not target abort
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire trdy_w = (
|
wire trdy_w = (
|
(state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && !pcir_fifo_data_err_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(state_wait && cnf_progress && ~target_abort_in)
|
(state_wait && cnf_progress && ~target_abort_in)
|
) ;
|
) ;
|
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire trdy_w_frm = (
|
wire trdy_w_frm = (
|
(state_transfere && ~disconect_wo_data_in) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
|
(state_transfere && disconect_wo_data_in && pci_irdy_reg_in) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in)
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (rw_cbe0 || !pcir_fifo_data_err_in))
|
) ;
|
) ;
|
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
wire trdy_w_frm_irdy = (
|
wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
|
(state_transfere && disconect_wo_data_in) ||
|
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in) ||
|
|
(state_backoff && ~bckp_trdy_in)
|
|
) ;
|
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_TRDY_CRIT pci_target_trdy_critical
|
PCI_TARGET32_TRDY_CRIT pci_target_trdy_critical
|
(
|
(
|
.trdy_w (trdy_w),
|
.trdy_w (trdy_w),
|
.trdy_w_frm (trdy_w_frm),
|
.trdy_w_frm (trdy_w_frm),
|
| Line 458... |
Line 526... |
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire stop_w = (
|
wire stop_w = (
|
(state_wait && target_abort_in) ||
|
(state_wait && target_abort_in) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
|
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
|
) ;
|
) ;
|
// if asserted, wait for deactivating the frame
|
// if asserted, wait for deactivating the frame
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire stop_w_frm = (
|
wire stop_w_frm = (
|
(state_backoff && ~bckp_stop_in)
|
(state_backoff && ~bckp_stop_in)
|
) ;
|
) ;
|
// if target abort or if disconnect without data (after data transfere)
|
// if target abort or if disconnect without data (after data transfere)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
|
wire stop_w_frm_irdy = (
|
wire stop_w_frm_irdy = (
|
(state_transfere && disconect_wo_data_in) ||
|
(state_transfere && (disconect_wo_data)) ||
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
) ;
|
) ;
|
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
|
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_STOP_CRIT pci_target_stop_critical
|
PCI_TARGET32_STOP_CRIT pci_target_stop_critical
|
(
|
(
|
| Line 487... |
Line 556... |
// if OK to respond and not target abort
|
// if OK to respond and not target abort
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire devs_w = (
|
wire devs_w = (
|
(addr_phase && config_access) ||
|
(addr_phase && config_access) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(state_wait && ~target_abort_in)
|
(state_wait && ~target_abort_in && !(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) )
|
) ;
|
) ;
|
|
|
// if not target abort (only during reads) or if asserted, wait for deactivating the frame
|
// if not target abort (only during reads) or if asserted, wait for deactivating the frame
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire devs_w_frm = (
|
wire devs_w_frm = (
|
(state_transfere && rw_cbe0) ||
|
(state_transfere && rw_cbe0) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
|
| Line 512... |
Line 582... |
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_devsel_out (pci_devsel_out)
|
.pci_devsel_out (pci_devsel_out)
|
);
|
);
|
|
|
// if address is claimed when read
|
// signal used in AD enable module with preserving the hierarchy because of minimum delay for critical inputs
|
// NO CRITICAL SIGNALS
|
assign pci_ad_en_out = (
|
wire ad_en_w = (
|
|
(addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
|
(state_wait && ~rw_cbe0)
|
(state_wait && ~rw_cbe0) ||
|
) ;
|
|
// if read
|
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
|
wire ad_en_w_frm = (
|
|
(state_transfere && ~rw_cbe0) ||
|
(state_transfere && ~rw_cbe0) ||
|
(state_backoff && ~rw_cbe0)
|
(state_backoff && ~rw_cbe0 && ~pci_frame_reg_in)
|
) ;
|
|
// AD enable module used for preserving the architecture because of minimum delay for critical inputs
|
|
PCI_TARGET32_AD_EN_CRIT pci_target_ad_enable_critical
|
|
(
|
|
.ad_en_w (ad_en_w),
|
|
.ad_en_w_frm (ad_en_w_frm),
|
|
.pci_frame_in (pci_frame_in),
|
|
.pci_ad_en_out (pci_ad_en_out)
|
|
);
|
);
|
|
|
wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ;
|
wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ;
|
|
|
// if cycle will progress or will not be stopped
|
// if cycle will progress or will not be stopped
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire ctrl_en_w = (
|
wire ctrl_en =
|
(~wbu_frame_en_in && fast_back_to_back) ||
|
/*(~wbu_frame_en_in && fast_back_to_back) ||*/
|
(addr_phase && config_access) ||
|
(addr_phase && config_access) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(state_wait) ||
|
(state_wait) ||
|
(state_transfere && ~pci_frame_reg_in) ||
|
(state_transfere && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ||
|
(state_backoff && ~pci_frame_reg_in)
|
(state_backoff && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ;
|
) ;
|
|
// if cycle is progressing
|
assign pci_trdy_en_out = ctrl_en ;
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
assign pci_stop_en_out = ctrl_en ;
|
wire ctrl_en_w_irdy = (
|
assign pci_devsel_en_out = ctrl_en ;
|
(state_transfere) ||
|
|
(state_backoff)
|
|
) ;
|
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
|
PCI_TARGET32_CTRL_EN_CRIT pci_target_control_enable_critical
|
|
(
|
|
.ctrl_en_w (ctrl_en_w),
|
|
.ctrl_en_w_irdy (ctrl_en_w_irdy),
|
|
.pci_irdy_in (pci_irdy_in),
|
|
.pci_trdy_en_out (pci_trdy_en_out),
|
|
.pci_stop_en_out (pci_stop_en_out),
|
|
.pci_devsel_en_out (pci_devsel_en_out)
|
|
);
|
|
|
|
// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
|
// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
|
// data are registered in io mux module - from fifo or medoum register
|
// data are registered in io mux module - from fifo or medoum register
|
reg bckp_trdy_reg ;
|
reg bckp_trdy_reg ;
|
// delayed indicators for states transfere and backoff
|
// delayed indicators for states transfere and backoff
|
| Line 573... |
Line 617... |
reg state_backoff_reg ;
|
reg state_backoff_reg ;
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
bckp_trdy_reg <= 1'b1 ;
|
bckp_trdy_reg <= #`FF_DELAY 1'b1 ;
|
state_transfere_reg <= 1'b0 ;
|
state_transfere_reg <= #`FF_DELAY 1'b0 ;
|
state_backoff_reg <= 1'b0 ;
|
state_backoff_reg <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
bckp_trdy_reg <= bckp_trdy_in ;
|
bckp_trdy_reg <= #`FF_DELAY bckp_trdy_in ;
|
state_transfere_reg <= state_transfere ;
|
state_transfere_reg <= #`FF_DELAY state_transfere ;
|
state_backoff_reg <= state_backoff ;
|
state_backoff_reg <= #`FF_DELAY state_backoff ;
|
end
|
end
|
end
|
end
|
|
|
// Read control signals assignments
|
// Read control signals assignments
|
assign
|
assign
|
fetch_pcir_fifo_out = (
|
fetch_pcir_fifo_out = (
|
(prepare_rd_fifo_data) ||
|
(prepare_rd_fifo_data) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
|
(bckp_trdy_en_in && ~bckp_trdy_reg && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
|
(bckp_trdy_en_in && ~pci_trdy_reg_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
|
) ;
|
) ;
|
|
|
// NO CRITICAL SIGNALS
|
assign ad_load_out = (state_wait) ;
|
wire tar_load_out_w = (state_wait) ;
|
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
assign ad_load_on_transfer_out = (bckp_trdy_en_in && ~rw_cbe0) ;
|
wire tar_load_out_w_irdy = (bckp_trdy_en_in && ~rw_cbe0) ;
|
|
// NO CRITICAL SIGNALS
|
assign load_medium_reg_out = (
|
wire load_med_reg_w = (
|
|
(prepare_rd_fifo_data) ||
|
(prepare_rd_fifo_data) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in)
|
(state_wait && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~target_abort_in) ||
|
) ;
|
(~pci_irdy_reg_in && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~pci_trdy_reg_in && bckp_trdy_en_in)
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
|
wire load_med_reg_w_irdy =
|
|
(bckp_trdy_en_in && ~bckp_trdy_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo) ;
|
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
|
PCI_TARGET32_LOAD_CRIT pci_target_load_critical
|
|
(
|
|
.tar_load_out_w (tar_load_out_w),
|
|
.tar_load_out_w_irdy (tar_load_out_w_irdy),
|
|
.load_med_reg_w (load_med_reg_w),
|
|
.load_med_reg_w_irdy (load_med_reg_w_irdy),
|
|
.pci_irdy_in (pci_irdy_in),
|
|
.pci_target_load_out (pci_target_load_out),
|
|
.load_medium_reg_out (load_medium_reg_out)
|
|
);
|
);
|
|
|
assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
|
assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
assign sel_conf_fifo_out = 1'b0 ;
|
|
`else
|
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
|
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
|
|
`endif
|
|
`else
|
|
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
|
|
`endif
|
|
|
assign fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
|
// NOT USED NOW, SINCE READ IS ASYNCHRONOUS
|
|
//assign fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
|
|
assign fetch_conf_out = 1'b0 ;
|
|
|
// Write control signals assignments
|
// Write control signals assignments
|
assign
|
assign
|
load_to_pciw_fifo_out = (
|
load_to_pciw_fifo_out = (
|
(state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
|
(state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
|
(state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo && ~disconect_wo_data_reg && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
|
(state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo /*&& ~disconect_wo_data_reg*/ && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
|
((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
|
((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
|
) ;
|
) ;
|
|
|
|
`ifdef HOST
|
|
`ifdef NO_CNF_IMAGE
|
|
assign load_to_conf_out = 1'b0 ;
|
|
`else
|
|
assign load_to_conf_out = (
|
|
(state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
|
|
(state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
|
|
) ;
|
|
`endif
|
|
`else
|
assign load_to_conf_out = (
|
assign load_to_conf_out = (
|
(state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
|
(state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
|
(state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
|
(state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
|
) ;
|
) ;
|
|
`endif
|
|
|
// General control sigal assignments
|
// General control sigal assignments
|
assign addr_phase_out = addr_phase ;
|
assign addr_phase_out = addr_phase ;
|
assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
|
assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
|
assign frame_reg_out = pci_frame_reg_in ;
|
assign frame_reg_out = pci_frame_reg_in ;
|
|
assign bckp_devsel_out = bckp_devsel_in ;
|
assign bckp_trdy_out = bckp_trdy_in ;
|
assign bckp_trdy_out = bckp_trdy_in ;
|
assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in) ;
|
assign bckp_stop_out = bckp_stop_in ;
|
|
assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in && bckp_trdy_en_in) ;
|
// request signal for delayed sinc. module
|
// request signal for delayed sinc. module
|
assign req_out = (state_wait && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request && ~target_abort_in) ;
|
reg master_will_request_read ;
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
master_will_request_read <= #`FF_DELAY 1'b0 ;
|
|
else
|
|
master_will_request_read <= #`FF_DELAY (state_wait || state_backoff) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request && ~target_abort_in ;
|
|
end
|
|
// MORE OPTIMIZED READS, but not easy to control in a testbench!
|
|
//assign req_out = master_will_request_read ;
|
|
assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ;
|
|
|
// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
|
// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
|
assign rdy_out = ~bckp_trdy_reg ;
|
assign rdy_out = ~bckp_trdy_reg ;
|
|
|
// data and address outputs assignments!
|
// data and address outputs assignments!
|
assign pci_ad_out = data_in ;
|
assign pci_ad_out = data_in ;
|
| Line 658... |
Line 722... |
assign bc_out = pci_cbe_reg_in ;
|
assign bc_out = pci_cbe_reg_in ;
|
assign bc0_out = rw_cbe0 ;
|
assign bc0_out = rw_cbe0 ;
|
|
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
