| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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| Line 702... |
Line 705... |
always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if ( reset_in )
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if ( reset_in )
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master_will_request_read <= #`FF_DELAY 1'b0 ;
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master_will_request_read <= #`FF_DELAY 1'b0 ;
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else
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else
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master_will_request_read <= #`FF_DELAY (state_wait || state_backoff) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request && ~target_abort_in ;
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master_will_request_read <= #`FF_DELAY ((state_wait && ~target_abort_in) || (state_backoff && ~target_abort_set_out)) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request ;
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end
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end
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// MORE OPTIMIZED READS, but not easy to control in a testbench!
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// MORE OPTIMIZED READS, but not easy to control in a testbench!
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//assign req_out = master_will_request_read ;
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//assign req_out = master_will_request_read ;
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assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ;
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assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ;
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