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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ;
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wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ;
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`else
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`else
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
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wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)
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(pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle
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// Write and read progresses are used for determining next state
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// Write and read progresses are used for determining next state
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wire write_progress = ( (norm_access_to_config_in) ||
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wire write_progress = ( (norm_access_to_config_in) ||
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(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
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wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
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(read_completed_in && wbw_fifo_empty_in) ) ;
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(read_completed_in && wbw_fifo_empty_in) ) ;
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`endif
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`endif
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`else
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`else
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
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wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)
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(pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle
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// Write and read progresses are used for determining next state
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// Write and read progresses are used for determining next state
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wire write_progress = ( (norm_access_to_config_in) ||
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wire write_progress = ( (norm_access_to_config_in) ||
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(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
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wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
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wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
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