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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target32_sm.v] - Diff between revs 51 and 55

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Rev 51 Rev 55
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/08/22 09:07:06  mihad
 
// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
 
//
// Revision 1.4  2002/02/19 16:32:37  mihad
// Revision 1.4  2002/02/19 16:32:37  mihad
// Modified testbench and fixed some bugs
// Modified testbench and fixed some bugs
//
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
// Repaired a few bugs, updated specification, added test bench files and design document
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) ;
 
 
/*----------------------------------------------------------------------------------------------------------------------
/*----------------------------------------------------------------------------------------------------------------------
Various parameters needed for state machine and other stuff
Various parameters needed for state machine and other stuff
----------------------------------------------------------------------------------------------------------------------*/
----------------------------------------------------------------------------------------------------------------------*/
parameter       S_IDLE          = `P_FSM_BITS'h0 ;
parameter       S_IDLE          = 3'b001 ;
parameter       S_WAIT          = `P_FSM_BITS'h1 ;
parameter       S_WAIT          = 3'b010 ;
parameter       S_TRANSFERE     = `P_FSM_BITS'h2 ;
parameter       S_TRANSFERE     = 3'b100 ;
 
 
 
 
/*==================================================================================================================
/*==================================================================================================================
System inputs.
System inputs.
==================================================================================================================*/
==================================================================================================================*/

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