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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/09/24 18:30:00 mihad
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// Changed state machine encoding to true one-hot
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//
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// Revision 1.5 2002/08/22 09:07:06 mihad
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// Revision 1.5 2002/08/22 09:07:06 mihad
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// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
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// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
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//
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`define P_FSM_BITS 2 // number of bits needed for FSM states
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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.state_transfere (sm_transfere),
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.state_transfere (sm_transfere),
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.state_default (state_default),
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.state_default (state_default),
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.clk_enable (pcit_sm_clk_en)
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.clk_enable (pcit_sm_clk_en)
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);
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);
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reg [(`P_FSM_BITS - 1):0] c_state ; //current state register
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reg [2:0] c_state ; //current state register
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reg [(`P_FSM_BITS - 1):0] n_state ; //next state input to current state register
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reg [2:0] n_state ; //next state input to current state register
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// state machine register control
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// state machine register control
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always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if (reset_in) // reset state machine to S_IDLE state
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if (reset_in) // reset state machine to S_IDLE state
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