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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target32_sm.v] - Diff between revs 2 and 6

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//////////////////////////////////////////////////////////////////////
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
 
// New project directory structure
 
//
//
//
 
 
`define FSM_BITS 2 // number of bits needed for FSM states
`define FSM_BITS 2 // number of bits needed for FSM states
 
 
 
 
`include "bus_commands.v"
`include "bus_commands.v"
`include "constants.v"
`include "constants.v"
 
`include "timescale.v"
 
 
module PCI_TARGET32_SM
module PCI_TARGET32_SM
(
(
    // system inputs
    // system inputs
    clk_in,
    clk_in,

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