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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/09/24 19:09:17 mihad
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// Number of state bits define was removed
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//
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// Revision 1.6 2002/09/24 18:30:00 mihad
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// Revision 1.6 2002/09/24 18:30:00 mihad
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// Changed state machine encoding to true one-hot
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// Changed state machine encoding to true one-hot
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//
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//
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// Revision 1.5 2002/08/22 09:07:06 mihad
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// Revision 1.5 2002/08/22 09:07:06 mihad
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// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
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// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
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// if not disconnect without data and not target abort (only during reads)
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// if not disconnect without data and not target abort (only during reads)
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// MUST BE ANDED WITH CRITICAL ~FRAME
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// MUST BE ANDED WITH CRITICAL ~FRAME
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wire trdy_w_frm = (
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wire trdy_w_frm = (
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (rw_cbe0 || !pcir_fifo_data_err_in))
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(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (!rw_cbe0 && !pcir_fifo_data_err_in))
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) ;
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) ;
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// if not disconnect without data and not target abort (only during reads)
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// if not disconnect without data and not target abort (only during reads)
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// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
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// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
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wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
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wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
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// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
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// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
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