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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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| Line 331... |
Line 334... |
assign pciu_conf_be_out = pcit_if_conf_be_out ;
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assign pciu_conf_be_out = pcit_if_conf_be_out ;
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assign pciu_conf_data_out = pcit_if_conf_data_out ;
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assign pciu_conf_data_out = pcit_if_conf_data_out ;
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// wishbone master state machine outputs
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// wishbone master state machine outputs
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wire wbm_sm_wb_read_done ;
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wire wbm_sm_wb_read_done ;
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wire wbm_sm_write_attempt ;
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wire wbm_sm_pcir_fifo_wenable_out ;
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wire wbm_sm_pcir_fifo_wenable_out ;
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wire [31:0] wbm_sm_pcir_fifo_data_out ;
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wire [31:0] wbm_sm_pcir_fifo_data_out ;
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wire [3:0] wbm_sm_pcir_fifo_be_out ;
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wire [3:0] wbm_sm_pcir_fifo_be_out ;
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wire [3:0] wbm_sm_pcir_fifo_control_out ;
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wire [3:0] wbm_sm_pcir_fifo_control_out ;
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wire wbm_sm_pciw_fifo_renable_out ;
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wire wbm_sm_pciw_fifo_renable_out ;
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| Line 378... |
Line 382... |
wire fifos_pciw_full_out ;
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wire fifos_pciw_full_out ;
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wire fifos_pciw_almost_empty_out ;
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wire fifos_pciw_almost_empty_out ;
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wire fifos_pciw_empty_out ;
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wire fifos_pciw_empty_out ;
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wire fifos_pciw_transaction_ready_out ;
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wire fifos_pciw_transaction_ready_out ;
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assign pciu_pciw_fifo_empty_out = fifos_pciw_empty_out ;
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assign pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt;
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// pcir_fifo_outputs
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// pcir_fifo_outputs
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wire [31:0] fifos_pcir_data_out ;
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wire [31:0] fifos_pcir_data_out ;
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wire [3:0] fifos_pcir_be_out ;
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wire [3:0] fifos_pcir_be_out ;
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wire [3:0] fifos_pcir_control_out ;
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wire [3:0] fifos_pcir_control_out ;
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wire fifos_pcir_almost_full_out ;
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wire fifos_pcir_full_out ;
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wire fifos_pcir_almost_empty_out ;
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wire fifos_pcir_almost_empty_out ;
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wire fifos_pcir_empty_out ;
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wire fifos_pcir_empty_out ;
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// delayed transaction logic outputs
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// delayed transaction logic outputs
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wire [31:0] del_sync_addr_out ;
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wire [31:0] del_sync_addr_out ;
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Line 414... |
wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ;
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wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ;
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wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ;
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wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ;
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wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ;
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wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ;
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wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ;
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wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ;
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wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ;
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wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ;
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wire wbm_sm_pcir_fifo_almost_full_in = fifos_pcir_almost_full_out ;
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wire wbm_sm_pcir_fifo_full_in = fifos_pcir_full_out ;
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wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ;
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wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ;
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wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ;
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wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ;
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wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ;
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wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ;
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wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;
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wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;
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wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;
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wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;
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| Line 438... |
Line 438... |
.pci_tar_be (wbm_sm_pci_tar_be), //in
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.pci_tar_be (wbm_sm_pci_tar_be), //in
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.pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in
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.pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in
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.pci_cache_line_size (wbm_sm_pci_cache_line_size), //in
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.pci_cache_line_size (wbm_sm_pci_cache_line_size), //in
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.cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in),
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.cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in),
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.wb_read_done_out (wbm_sm_wb_read_done), //out
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.wb_read_done_out (wbm_sm_wb_read_done), //out
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.w_attempt (wbm_sm_write_attempt), //out
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.pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out),
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.pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out),
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.pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out),
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.pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out),
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.pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out),
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.pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out),
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.pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out),
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.pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out),
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.pcir_fifo_almost_full_in (wbm_sm_pcir_fifo_almost_full_in),
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.pcir_fifo_full_in (wbm_sm_pcir_fifo_full_in),
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.pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out),
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.pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out),
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.pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in),
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.pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in),
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.pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in),
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.pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in),
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.pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in),
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.pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in),
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.pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in),
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.pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in),
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| Line 516... |
Line 515... |
.pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!!
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.pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!!
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.pcir_data_out (fifos_pcir_data_out), //for PCI Target !!!
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.pcir_data_out (fifos_pcir_data_out), //for PCI Target !!!
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.pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!
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.pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!
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.pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!
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.pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!
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.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
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.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
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.pcir_almost_full_out (fifos_pcir_almost_full_out),
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.pcir_almost_full_out (),
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.pcir_full_out (fifos_pcir_full_out),
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.pcir_full_out (),
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.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
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.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_transaction_ready_out ()
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.pcir_transaction_ready_out ()
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) ;
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) ;
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