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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ;
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wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ;
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wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ;
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wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ;
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wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ;
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wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ;
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wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ;
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wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ;
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wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ;
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wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ;
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wire fifos_pciw_flush_in = 1'b0 ;
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//wire fifos_pciw_flush_in = 1'b0 ; // flush not used for write fifo
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// PCIR_FIFO inputs
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// PCIR_FIFO inputs
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wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ;
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wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ;
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wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ;
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wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ;
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wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ;
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wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ;
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.pciw_control_in (fifos_pciw_control_in), //for PCI Target !!!
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.pciw_control_in (fifos_pciw_control_in), //for PCI Target !!!
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.pciw_renable_in (fifos_pciw_renable_in),
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.pciw_renable_in (fifos_pciw_renable_in),
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.pciw_addr_data_out (fifos_pciw_addr_data_out),
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.pciw_addr_data_out (fifos_pciw_addr_data_out),
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.pciw_cbe_out (fifos_pciw_cbe_out),
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.pciw_cbe_out (fifos_pciw_cbe_out),
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.pciw_control_out (fifos_pciw_control_out),
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.pciw_control_out (fifos_pciw_control_out),
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.pciw_flush_in (fifos_pciw_flush_in),
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// .pciw_flush_in (fifos_pciw_flush_in), // flush not used for write fifo
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.pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!!
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.pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!!
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.pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!!
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.pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!!
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.pciw_full_out (fifos_pciw_full_out), //for PCI Target !!!
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.pciw_full_out (fifos_pciw_full_out), //for PCI Target !!!
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.pciw_almost_empty_out (fifos_pciw_almost_empty_out),
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.pciw_almost_empty_out (fifos_pciw_almost_empty_out),
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.pciw_empty_out (fifos_pciw_empty_out),
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.pciw_empty_out (fifos_pciw_empty_out),
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