| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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//
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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// Added some testcases, removed un-needed fifo signals
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//
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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| Line 151... |
Line 154... |
pciu_conf_be_out,
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pciu_conf_be_out,
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pciu_conf_data_out,
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pciu_conf_data_out,
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pciu_conf_select_out,
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pciu_conf_select_out,
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pciu_pci_drcomp_pending_out,
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pciu_pci_drcomp_pending_out,
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pciu_pciw_fifo_empty_out
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pciu_pciw_fifo_empty_out
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`ifdef PCI_BIST
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,
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// debug chain signals
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SO ,
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SI ,
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shift_DR ,
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capture_DR ,
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extest ,
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tck
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`endif
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);
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);
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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pci_clock_in ;
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pci_clock_in ;
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| Line 248... |
Line 262... |
output [31:0] pciu_conf_data_out ;
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output [31:0] pciu_conf_data_out ;
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output pciu_pci_drcomp_pending_out ;
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output pciu_pci_drcomp_pending_out ;
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output pciu_pciw_fifo_empty_out ;
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output pciu_pciw_fifo_empty_out ;
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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BIST debug chain port signals
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-----------------------------------------------------*/
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output SO ;
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input SI ;
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input shift_DR ;
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input capture_DR ;
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input extest ;
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input tck ;
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`endif
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// pci target state machine and interface outputs
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// pci target state machine and interface outputs
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wire pcit_sm_trdy_out ;
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wire pcit_sm_trdy_out ;
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wire pcit_sm_stop_out ;
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wire pcit_sm_stop_out ;
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wire pcit_sm_devsel_out ;
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wire pcit_sm_devsel_out ;
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| Line 525... |
Line 551... |
.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
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.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
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.pcir_full_out (),
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.pcir_full_out (),
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.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
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.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_transaction_ready_out ()
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.pcir_transaction_ready_out ()
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`ifdef PCI_BIST
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,
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.SO (SO),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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) ;
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) ;
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// delayed transaction logic inputs
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// delayed transaction logic inputs
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wire del_sync_req_in = pcit_if_req_out ;
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wire del_sync_req_in = pcit_if_req_out ;
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wire del_sync_comp_in = wbm_sm_wb_read_done ;
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wire del_sync_comp_in = wbm_sm_wb_read_done ;
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