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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target_unit.v] - Diff between revs 62 and 63
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Rev 63 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/10/08 17:17:05 mihad
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// Added BIST signals for RAMs.
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//
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// Revision 1.6 2002/09/25 15:53:52 mihad
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// Revision 1.6 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Revision 1.5 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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// Added some testcases, removed un-needed fifo signals
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Line 158... |
Line 161... |
pciu_pciw_fifo_empty_out
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pciu_pciw_fifo_empty_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst ,
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SO ,
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SO ,
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SI ,
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SI ,
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shift_DR ,
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shift_DR ,
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capture_DR ,
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capture_DR ,
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extest ,
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extest ,
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Line 266... |
Line 270... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input trst ;
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output SO ;
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output SO ;
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input SI ;
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input SI ;
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input shift_DR ;
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input shift_DR ;
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input capture_DR ;
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input capture_DR ;
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input extest ;
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input extest ;
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Line 554... |
Line 559... |
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_transaction_ready_out ()
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.pcir_transaction_ready_out ()
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.trst (trst),
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.SO (SO),
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.SO (SO),
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.SI (SI),
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.SI (SI),
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.shift_DR (shift_DR),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.extest (extest),
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