| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2002/10/11 10:09:01 mihad
|
|
// Added additional testcase and changed rst name in BIST to trst
|
|
//
|
// Revision 1.7 2002/10/08 17:17:05 mihad
|
// Revision 1.7 2002/10/08 17:17:05 mihad
|
// Added BIST signals for RAMs.
|
// Added BIST signals for RAMs.
|
//
|
//
|
// Revision 1.6 2002/09/25 15:53:52 mihad
|
// Revision 1.6 2002/09/25 15:53:52 mihad
|
// Removed all logic from asynchronous reset network
|
// Removed all logic from asynchronous reset network
|
| Line 161... |
Line 164... |
pciu_pciw_fifo_empty_out
|
pciu_pciw_fifo_empty_out
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
trst ,
|
scanb_rst, // bist scan reset
|
SO ,
|
scanb_clk, // bist scan clock
|
SI ,
|
scanb_si, // bist scan serial in
|
shift_DR ,
|
scanb_so, // bist scan serial out
|
capture_DR ,
|
scanb_sen // bist scan shift enable
|
extest ,
|
|
tck
|
|
`endif
|
`endif
|
);
|
);
|
|
|
input reset_in,
|
input reset_in,
|
wb_clock_in,
|
wb_clock_in,
|
| Line 270... |
Line 271... |
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
/*-----------------------------------------------------
|
/*-----------------------------------------------------
|
BIST debug chain port signals
|
BIST debug chain port signals
|
-----------------------------------------------------*/
|
-----------------------------------------------------*/
|
input trst ;
|
input scanb_rst; // bist scan reset
|
output SO ;
|
input scanb_clk; // bist scan clock
|
input SI ;
|
input scanb_si; // bist scan serial in
|
input shift_DR ;
|
output scanb_so; // bist scan serial out
|
input capture_DR ;
|
input scanb_sen; // bist scan shift enable
|
input extest ;
|
|
input tck ;
|
|
`endif
|
`endif
|
|
|
|
|
// pci target state machine and interface outputs
|
// pci target state machine and interface outputs
|
wire pcit_sm_trdy_out ;
|
wire pcit_sm_trdy_out ;
|
| Line 559... |
Line 558... |
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
|
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
|
.pcir_transaction_ready_out ()
|
.pcir_transaction_ready_out ()
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.trst (trst),
|
.scanb_rst (scanb_rst),
|
.SO (SO),
|
.scanb_clk (scanb_clk),
|
.SI (SI),
|
.scanb_si (scanb_si),
|
.shift_DR (shift_DR),
|
.scanb_so (scanb_so),
|
.capture_DR (capture_DR),
|
.scanb_sen (scanb_sen)
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
`endif
|
) ;
|
) ;
|
|
|
// delayed transaction logic inputs
|
// delayed transaction logic inputs
|
wire del_sync_req_in = pcit_if_req_out ;
|
wire del_sync_req_in = pcit_if_req_out ;
|
