URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_tpram.v] - Diff between revs 49 and 60

Rev 49	Rev 60
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/08/19 16:51:36 mihad`
	`// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives`
	`//`
`// Revision 1.1 2002/02/01 14:43:31 mihad`	`// Revision 1.1 2002/02/01 14:43:31 mihad`
`// * empty log message *`	`// * empty log message *`
`//`	`//`
`//`	`//`

Line 121...	Line 124...

`//`	`//`
`// Internal wires and registers`	`// Internal wires and registers`
`//`	`//`

	`ifdef PCI_VS_STP
	`define PCI_PCI_RAM_SELECTED
	`vs_hdtp_64x40 i_vs_hdtp_64x40`
	`(`
	`.RCK (clk_b),`
	`.WCK (clk_a),`
	`.RADR (addr_b),`
	`.WADR (addr_a),`
	`.DI (di_a),`
	`.DOUT (do_b),`
	`.REN (1'b0),`
	`.WEN (!we_a)`
	`);`

	`assign do_a = 0 ;`
	`endif

`ifdef PCI_ARTISAN_SDP	`ifdef PCI_ARTISAN_SDP
`define PCI_PCI_RAM_SELECTED	`define PCI_PCI_RAM_SELECTED
`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`