| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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//
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// Revision 1.2 2002/08/19 16:51:36 mihad
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// Revision 1.2 2002/08/19 16:51:36 mihad
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// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
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// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
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//
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//
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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// *** empty log message ***
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| Line 92... |
Line 95... |
we_b,
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we_b,
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oe_b,
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oe_b,
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addr_b,
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addr_b,
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di_b,
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di_b,
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do_b
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do_b
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`ifdef PCI_BIST
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,
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// debug chain signals
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SO,
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SI,
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shift_DR,
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capture_DR,
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extest,
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tck
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`endif
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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| Line 120... |
Line 133... |
input oe_b; // Output enable input
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input oe_b; // Output enable input
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input [aw-1:0] addr_b; // address bus inputs
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input [aw-1:0] addr_b; // address bus inputs
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input [dw-1:0] di_b; // input data bus
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input [dw-1:0] di_b; // input data bus
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output [dw-1:0] do_b; // output data bus
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output [dw-1:0] do_b; // output data bus
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`ifdef PCI_BIST
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// debug chain signals
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output SO ;
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input SI ;
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input shift_DR ;
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input capture_DR ;
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input extest ;
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input tck ;
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`endif
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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`ifdef PCI_VS_STP
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`ifdef PCI_VS_STP
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`define PCI_PCI_RAM_SELECTED
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`define PCI_PCI_RAM_SELECTED
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`ifdef PCI_BIST
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vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
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`else
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vs_hdtp_64x40 i_vs_hdtp_64x40
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vs_hdtp_64x40 i_vs_hdtp_64x40
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`endif
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(
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(
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.RCK (clk_b),
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.RCK (clk_b),
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.WCK (clk_a),
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.WCK (clk_a),
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.RADR (addr_b),
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.RADR (addr_b),
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.WADR (addr_a),
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.WADR (addr_a),
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.DI (di_a),
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.DI (di_a),
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.DOUT (do_b),
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.DOUT (do_b),
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.REN (1'b0),
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.REN (1'b0),
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.WEN (!we_a)
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.WEN (!we_a)
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`ifdef PCI_BIST
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,
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// reset
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.rst (rst_a),
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|
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// debug chain signals
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.SO (SO),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR (capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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);
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);
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|
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assign do_a = 0 ;
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assign do_a = 0 ;
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`endif
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`endif
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|
|
