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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_tpram.v] - Diff between revs 62 and 63
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| Rev 62 |
Rev 63 |
| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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//
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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//
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//
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// Revision 1.2 2002/08/19 16:51:36 mihad
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// Revision 1.2 2002/08/19 16:51:36 mihad
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// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
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// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
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| Line 98... |
Line 101... |
di_b,
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di_b,
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do_b
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do_b
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst,
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SO,
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SO,
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SI,
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SI,
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shift_DR,
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shift_DR,
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capture_DR,
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capture_DR,
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extest,
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extest,
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Line 139... |
input [dw-1:0] di_b; // input data bus
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input [dw-1:0] di_b; // input data bus
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output [dw-1:0] do_b; // output data bus
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output [dw-1:0] do_b; // output data bus
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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// debug chain signals
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// debug chain signals
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input trst ;
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output SO ;
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output SO ;
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input SI ;
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input SI ;
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input shift_DR ;
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input shift_DR ;
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input capture_DR ;
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input capture_DR ;
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input extest ;
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input extest ;
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| Line 166... |
Line 171... |
.REN (1'b0),
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.REN (1'b0),
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.WEN (!we_a)
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.WEN (!we_a)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// reset
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// reset
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.rst (rst_a),
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.trst (trst),
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// debug chain signals
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// debug chain signals
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.SO (SO),
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.SO (SO),
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.SI (SI),
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.SI (SI),
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.shift_DR (shift_DR),
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.shift_DR (shift_DR),
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