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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.4 2002/10/08 17:17:06 mihad
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// Revision 1.4 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Revision 1.3 2002/09/30 17:22:27 mihad
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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| Line 101... |
Line 104... |
di_b,
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di_b,
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do_b
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do_b
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst,
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scanb_rst, // bist scan reset
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SO,
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scanb_clk, // bist scan clock
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SI,
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scanb_si, // bist scan serial in
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shift_DR,
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scanb_so, // bist scan serial out
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capture_DR,
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scanb_sen // bist scan shift enable
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extest,
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tck
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`endif
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`endif
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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Line 140... |
input [dw-1:0] di_b; // input data bus
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input [dw-1:0] di_b; // input data bus
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output [dw-1:0] do_b; // output data bus
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output [dw-1:0] do_b; // output data bus
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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// debug chain signals
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// debug chain signals
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input trst ;
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input scanb_rst; // bist scan reset
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output SO ;
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input scanb_clk; // bist scan clock
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input SI ;
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input scanb_si; // bist scan serial in
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input shift_DR ;
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output scanb_so; // bist scan serial out
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input capture_DR ;
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input scanb_sen; // bist scan shift enable
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input extest ;
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input tck ;
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`endif
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`endif
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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| Line 170... |
Line 169... |
.DOUT (do_b),
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.DOUT (do_b),
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.REN (1'b0),
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.REN (1'b0),
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.WEN (!we_a)
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.WEN (!we_a)
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// reset
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.trst (trst),
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// debug chain signals
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// debug chain signals
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.SO (SO),
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.scanb_rst (scanb_rst),
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.SI (SI),
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.scanb_clk (scanb_clk),
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.shift_DR (shift_DR),
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.scanb_si (scanb_si),
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.capture_DR (capture_DR),
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.scanb_so (scanb_so),
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.extest (extest),
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.scanb_sen (scanb_sen)
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.tck (tck)
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`endif
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`endif
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);
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);
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assign do_a = 0 ;
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assign do_a = 0 ;
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`endif
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`endif
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