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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_tpram.v] - Diff between revs 67 and 68

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Rev 67 Rev 68
Line 60... Line 60...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2002/10/17 22:51:08  tadejm
 
// Changed BIST signals for RAMs.
 
//
// Revision 1.5  2002/10/11 10:09:01  mihad
// Revision 1.5  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
// Added additional testcase and changed rst name in BIST to trst
//
//
// Revision 1.4  2002/10/08 17:17:06  mihad
// Revision 1.4  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
// Added BIST signals for RAMs.
Line 108... Line 111...
    // debug chain signals
    // debug chain signals
    scanb_rst,      // bist scan reset
    scanb_rst,      // bist scan reset
    scanb_clk,      // bist scan clock
    scanb_clk,      // bist scan clock
    scanb_si,       // bist scan serial in
    scanb_si,       // bist scan serial in
    scanb_so,       // bist scan serial out
    scanb_so,       // bist scan serial out
    scanb_sen       // bist scan shift enable
    scanb_en        // bist scan shift enable
`endif
`endif
);
);
 
 
//
//
// Default address and data buses width
// Default address and data buses width
Line 144... Line 147...
// debug chain signals
// debug chain signals
input   scanb_rst;      // bist scan reset
input   scanb_rst;      // bist scan reset
input   scanb_clk;      // bist scan clock
input   scanb_clk;      // bist scan clock
input   scanb_si;       // bist scan serial in
input   scanb_si;       // bist scan serial in
output  scanb_so;       // bist scan serial out
output  scanb_so;       // bist scan serial out
input   scanb_sen;      // bist scan shift enable
input   scanb_en;       // bist scan shift enable
`endif
`endif
 
 
//
//
// Internal wires and registers
// Internal wires and registers
//
//
Line 174... Line 177...
            // debug chain signals
            // debug chain signals
            .scanb_rst  (scanb_rst),
            .scanb_rst  (scanb_rst),
            .scanb_clk  (scanb_clk),
            .scanb_clk  (scanb_clk),
            .scanb_si   (scanb_si),
            .scanb_si   (scanb_si),
            .scanb_so   (scanb_so),
            .scanb_so   (scanb_so),
            .scanb_sen  (scanb_sen)
            .scanb_en   (scanb_en)
        `endif
        `endif
        );
        );
 
 
    assign do_a = 0 ;
    assign do_a = 0 ;
`endif
`endif

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