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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_user_constants.v] - Diff between revs 45 and 60

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Rev 45 Rev 60
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/08/13 11:03:53  mihad
 
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
 
//
// Revision 1.2  2002/03/05 11:53:47  mihad
// Revision 1.2  2002/03/05 11:53:47  mihad
// Added some testcases, removed un-needed fifo signals
// Added some testcases, removed un-needed fifo signals
//
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
// *** empty log message ***
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`else
`else
    `define PCI_FIFO_RAM_ADDR_LENGTH 4      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define PCI_FIFO_RAM_ADDR_LENGTH 4      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 7       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 7       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
//    `define WB_ARTISAN_SDP
//    `define WB_ARTISAN_SDP
//    `define PCI_ARTISAN_SDP
//    `define PCI_ARTISAN_SDP
 
//    `define PCI_VS_STP
 
//    `define WB_VS_STP
`endif
`endif
 
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
`define ACTIVE_LOW_OE

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