| Line 125... |
Line 125... |
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FFs for registered empty and full flags
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// FFs for registered empty and full flags
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reg empty ;
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wire empty ;
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reg full ;
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wire full ;
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// registered almost_empty and almost_full flags
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// registered almost_empty and almost_full flags
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reg almost_empty ;
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wire almost_empty ;
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reg almost_full ;
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wire almost_full ;
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// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && ~full ;
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wire wallow = wenable_in && !full ;
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// write allow output assignment
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// write allow output assignment
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assign wallow_out = wallow ;
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assign wallow_out = wallow ;
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// read allow wire
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// read allow wire
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| Line 145... |
Line 145... |
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// full output assignment
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// full output assignment
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assign full_out = full ;
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assign full_out = full ;
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// almost full output assignment
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// almost full output assignment
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assign almost_full_out = almost_full && ~full ;
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assign almost_full_out = almost_full && !full ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in /*|| flush_in*/ ; // flush not used for write fifo
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wire clear = reset_in /*|| flush_in*/ ; // flush not used for write fifo
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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| Line 159... |
Line 159... |
wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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else
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else
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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end
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end
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reg stretched_empty ;
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wire stretched_empty ;
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always@(posedge rclock_in or posedge clear)
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begin
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wire stretched_empty_flop_i = empty && ~wclock_nempty_detect ;
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if(clear)
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stretched_empty <= #`FF_DELAY 1'b1 ;
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meta_flop #(1) i_meta_flop_stretched_empty
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else
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(
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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.rst_i (clear),
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end
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.clk_i (rclock_in),
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.ld_i (1'b0),
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.ld_val_i (1'b0),
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.en_i (1'b1),
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.d_i (stretched_empty_flop_i),
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.meta_q_o (stretched_empty)
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) ;
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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assign empty_out = empty || stretched_empty ;
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assign empty_out = empty || stretched_empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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// rallow output assignment
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assign rallow_out = rallow ;
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assign rallow_out = rallow ;
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// almost empty output assignment
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// almost empty output assignment
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assign almost_empty_out = almost_empty && ~empty && ~stretched_empty ;
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assign almost_empty_out = almost_empty && !empty && !stretched_empty ;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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| Line 353... |
Line 359... |
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Registered two left control:
|
Registered two left control:
|
registered two left is set on rising edge of write clock when three locations are left in fifo and another is written to it.
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registered two left is set on rising edge of write clock when three locations are left in fifo and another is written to it.
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it's kept high until something is read/written from/to fifo.
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it's kept high until something is read/written from/to fifo.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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reg two_left_out ;
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wire comb_full = wgrey_next == rgrey_addr ;
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wire comb_full = wgrey_next == rgrey_addr ;
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wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
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wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
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wire comb_two_left = wgrey_next == rgrey_minus2 ;
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wire comb_two_left = wgrey_next == rgrey_minus2 ;
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wire comb_three_left = wgrey_next == rgrey_minus3 ;
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wire comb_three_left = wgrey_next == rgrey_minus3 ;
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//combinatorial input to Registered full FlipFlop
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//combinatorial input to Registered full FlipFlop
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wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
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wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
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|
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always@(posedge wclock_in or posedge clear)
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meta_flop #(0) i_meta_flop_full
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begin
|
(
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if (clear)
|
.rst_i (clear),
|
full <= #`FF_DELAY 1'b0 ;
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.clk_i (wclock_in),
|
else
|
.ld_i (1'b0),
|
full <= #`FF_DELAY reg_full ;
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.ld_val_i (1'b0),
|
end
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.en_i (1'b1),
|
|
.d_i (reg_full),
|
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.meta_q_o (full)
|
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) ;
|
|
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// input for almost full flip flop
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// input for almost full flip flop
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wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
|
wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
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|
|
always@(posedge clear or posedge wclock_in)
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meta_flop #(0) i_meta_flop_almost_full
|
begin
|
(
|
if (clear)
|
.rst_i (clear),
|
almost_full <= #`FF_DELAY 1'b0 ;
|
.clk_i (wclock_in),
|
else
|
.ld_i (1'b0),
|
almost_full <= #`FF_DELAY reg_almost_full_in ;
|
.ld_val_i (1'b0),
|
end
|
.en_i (1'b1),
|
|
.d_i (reg_almost_full_in),
|
|
.meta_q_o (almost_full)
|
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) ;
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|
|
wire reg_two_left_in = wallow && comb_three_left || comb_two_left ;
|
wire reg_two_left_in = wallow && comb_three_left || comb_two_left ;
|
|
|
always@(posedge clear or posedge wclock_in)
|
meta_flop #(0) i_meta_flop_two_left
|
begin
|
(
|
if (clear)
|
.rst_i (clear),
|
two_left_out <= #`FF_DELAY 1'b0 ;
|
.clk_i (wclock_in),
|
else
|
.ld_i (1'b0),
|
two_left_out <= #`FF_DELAY reg_two_left_in ;
|
.ld_val_i (1'b0),
|
end
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.en_i (1'b1),
|
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.d_i (reg_two_left_in),
|
|
.meta_q_o (two_left_out)
|
|
) ;
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Registered empty control:
|
Registered empty control:
|
registered empty is set on rising edge of rclock_in,
|
registered empty is set on rising edge of rclock_in,
|
when only one location is used in and read from fifo. It's kept high until something is written to FIFO, which is registered on
|
when only one location is used in and read from fifo. It's kept high until something is written to FIFO, which is registered on
|
| Line 408... |
Line 422... |
wire comb_two_used = rgrey_next == wgrey_minus1 ;
|
wire comb_two_used = rgrey_next == wgrey_minus1 ;
|
|
|
// combinatorial input for registered emty FlipFlop
|
// combinatorial input for registered emty FlipFlop
|
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
|
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
|
|
|
always@(posedge rclock_in or posedge clear)
|
meta_flop #(1) i_meta_flop_empty
|
begin
|
(
|
if (clear)
|
.rst_i (clear),
|
empty <= #`FF_DELAY 1'b1 ;
|
.clk_i (rclock_in),
|
else
|
.ld_i (1'b0),
|
empty <= #`FF_DELAY reg_empty ;
|
.ld_val_i (1'b0),
|
end
|
.en_i (1'b1),
|
|
.d_i (reg_empty),
|
|
.meta_q_o (empty)
|
|
) ;
|
|
|
// input for almost empty flip flop
|
// input for almost empty flip flop
|
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
|
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
|
always@(posedge clear or posedge rclock_in)
|
|
begin
|
meta_flop #(0) i_meta_flop_almost_empty
|
if (clear)
|
(
|
almost_empty <= #`FF_DELAY 1'b0 ;
|
.rst_i (clear),
|
else
|
.clk_i (rclock_in),
|
almost_empty <= #`FF_DELAY reg_almost_empty ;
|
.ld_i (1'b0),
|
end
|
.ld_val_i (1'b0),
|
|
.en_i (1'b1),
|
|
.d_i (reg_almost_empty),
|
|
.meta_q_o (almost_empty)
|
|
) ;
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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