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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_fifo_control.v] - Diff between revs 59 and 66
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| Rev 59 |
Rev 66 |
| Line 420... |
Line 420... |
wire comb_almost_empty = rgrey_next == wgrey_addr ;
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wire comb_almost_empty = rgrey_next == wgrey_addr ;
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wire comb_empty = rgrey_addr == wgrey_addr ;
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wire comb_empty = rgrey_addr == wgrey_addr ;
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wire comb_two_used = rgrey_next == wgrey_minus1 ;
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wire comb_two_used = rgrey_next == wgrey_minus1 ;
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// combinatorial input for registered emty FlipFlop
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// combinatorial input for registered emty FlipFlop
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wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
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//wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
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wire reg_empty = (rallow && almost_empty) || comb_empty ;
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meta_flop #(1) i_meta_flop_empty
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meta_flop #(1) i_meta_flop_empty
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(
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(
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.rst_i (clear),
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.rst_i (clear),
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.clk_i (rclock_in),
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.clk_i (rclock_in),
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