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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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//
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// Revision 1.4 2002/03/05 11:53:47 mihad
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// Revision 1.4 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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// Added some testcases, removed un-needed fifo signals
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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end
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end
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// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
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// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
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// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
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// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
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// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
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// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
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reg pciw_transaction_ready_out ;
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always@(posedge wb_clock_in or posedge pciw_clear)
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wire pciw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
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begin
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meta_flop #(0) i_meta_flop_transaction_ready
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if (pciw_clear)
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(
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pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
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.rst_i (pciw_clear),
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else
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.clk_i (wb_clock_in),
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if ( out_count_en )
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.ld_i (out_count_en),
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pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
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.ld_val_i (1'b0),
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else
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.en_i (1'b1),
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pciw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
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.d_i (pciw_transaction_ready_flop_i),
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end
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.meta_q_o (pciw_transaction_ready_out)
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) ;
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assign pcir_transaction_ready_out = 1'b0 ;
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assign pcir_transaction_ready_out = 1'b0 ;
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endmodule
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endmodule
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