| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.7 2002/10/08 17:17:06 mihad
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// Revision 1.7 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.6 2002/09/30 16:03:04 mihad
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// Revision 1.6 2002/09/30 16:03:04 mihad
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// Added meta flop module for easier meta stable FF identification during synthesis
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// Added meta flop module for easier meta stable FF identification during synthesis
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| Line 106... |
Line 109... |
pcir_transaction_ready_out
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pcir_transaction_ready_out
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|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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trst ,
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scanb_rst, // bist scan reset
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SO ,
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scanb_clk, // bist scan clock
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SI ,
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scanb_si, // bist scan serial in
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shift_DR ,
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scanb_so, // bist scan serial out
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capture_DR ,
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scanb_sen // bist scan shift enable
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extest ,
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tck
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`endif
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`endif
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) ;
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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System inputs:
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| Line 228... |
Line 229... |
|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input trst ;
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input scanb_rst; // bist scan reset
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output SO ;
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input scanb_clk; // bist scan clock
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input SI ;
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input scanb_si; // bist scan serial in
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input shift_DR ;
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output scanb_so; // bist scan serial out
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input capture_DR ;
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input scanb_sen; // bist scan shift enable
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input extest ;
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input tck ;
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`endif
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`endif
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Address length parameters:
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Address length parameters:
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PCIW_DEPTH = defines PCIW_FIFO depth
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PCIW_DEPTH = defines PCIW_FIFO depth
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| Line 358... |
Line 357... |
|
|
wire pciw_read_enable = 1'b1 ;
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wire pciw_read_enable = 1'b1 ;
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wire pcir_read_enable = 1'b1 ;
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wire pcir_read_enable = 1'b1 ;
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|
|
`ifdef PCI_BIST
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`ifdef PCI_BIST
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wire SO_internal ; // wires for connection of debug ports on two rams
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wire scanb_so_internal ; // wires for connection of debug ports on two rams
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wire SI_internal = SO_internal ;
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wire scanb_si_internal = scanb_so_internal ;
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`endif
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`endif
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|
|
// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
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// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
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PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
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PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
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(
|
(
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| Line 386... |
Line 385... |
.di_b(40'h00_0000_0000),
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.di_b(40'h00_0000_0000),
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.do_b(dpram_portB_output)
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.do_b(dpram_portB_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.trst (trst),
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.scanb_rst (scanb_rst),
|
.SO (SO_internal),
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.scanb_clk (scanb_clk),
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.SI (SI),
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.scanb_si (scanb_si),
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.shift_DR (shift_DR),
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.scanb_so (scanb_so_internal),
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.capture_DR (capture_DR),
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.scanb_sen (scanb_sen)
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.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
`endif
|
);
|
);
|
|
|
PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
|
PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
|
(
|
(
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| Line 419... |
Line 416... |
.di_b(40'h00_0000_0000),
|
.di_b(40'h00_0000_0000),
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.do_b(dpram_portA_output)
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.do_b(dpram_portA_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.trst (trst),
|
.scanb_rst (scanb_rst),
|
.SO (SO),
|
.scanb_clk (scanb_clk),
|
.SI (SI_internal),
|
.scanb_si (scanb_si_internal),
|
.shift_DR (shift_DR),
|
.scanb_so (scanb_so),
|
.capture_DR (capture_DR),
|
.scanb_sen (scanb_sen)
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
`endif
|
);
|
);
|
|
|
`else // RAM blocks sharing between two fifos
|
`else // RAM blocks sharing between two fifos
|
|
|
| Line 484... |
Line 479... |
.di_b(dpram_portB_input),
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.di_b(dpram_portB_input),
|
.do_b(dpram_portB_output)
|
.do_b(dpram_portB_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.trst (trst),
|
.scanb_rst (scanb_rst),
|
.SO (SO),
|
.scanb_clk (scanb_clk),
|
.SI (SI),
|
.scanb_si (scanb_si),
|
.shift_DR (shift_DR),
|
.scanb_so (scanb_so),
|
.capture_DR (capture_DR),
|
.scanb_sen (scanb_sen)
|
.extest (extest),
|
|
.tck (tck)
|
|
`endif
|
`endif
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
