| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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//
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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//
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//
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// Revision 1.7 2002/10/08 17:17:06 mihad
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// Revision 1.7 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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| Line 113... |
Line 116... |
// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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scanb_rst, // bist scan reset
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scanb_clk, // bist scan clock
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scanb_clk, // bist scan clock
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scanb_si, // bist scan serial in
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scanb_si, // bist scan serial in
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scanb_so, // bist scan serial out
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scanb_so, // bist scan serial out
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scanb_sen // bist scan shift enable
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scanb_en // bist scan shift enable
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`endif
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`endif
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) ;
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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System inputs:
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| Line 233... |
Line 236... |
-----------------------------------------------------*/
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-----------------------------------------------------*/
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input scanb_rst; // bist scan reset
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input scanb_rst; // bist scan reset
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input scanb_clk; // bist scan clock
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input scanb_clk; // bist scan clock
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input scanb_si; // bist scan serial in
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input scanb_si; // bist scan serial in
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output scanb_so; // bist scan serial out
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output scanb_so; // bist scan serial out
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input scanb_sen; // bist scan shift enable
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Address length parameters:
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Address length parameters:
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PCIW_DEPTH = defines PCIW_FIFO depth
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PCIW_DEPTH = defines PCIW_FIFO depth
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| Line 389... |
Line 392... |
,
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,
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so_internal),
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.scanb_so (scanb_so_internal),
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.scanb_sen (scanb_sen)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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|
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PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
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PCI_TPRAM #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
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(
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(
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| Line 420... |
Line 423... |
,
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,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si_internal),
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.scanb_si (scanb_si_internal),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so),
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.scanb_sen (scanb_sen)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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|
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`else // RAM blocks sharing between two fifos
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`else // RAM blocks sharing between two fifos
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|
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| Line 483... |
Line 486... |
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_so),
|
.scanb_so (scanb_so),
|
.scanb_sen (scanb_sen)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
